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Diffstat (limited to 'software/lib/util.c')
| -rw-r--r-- | software/lib/util.c | 128 |
1 files changed, 128 insertions, 0 deletions
diff --git a/software/lib/util.c b/software/lib/util.c new file mode 100644 index 0000000..104f2b6 --- /dev/null +++ b/software/lib/util.c @@ -0,0 +1,128 @@ +/* + * spreadspace avr utils + * + * + * Copyright (C) 2013 Christian Pointner <equinox@spreadspace.org> + * + * This file is part of spreadspace avr utils. + * + * spreadspace avr utils is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * any later version. + * + * spreadspace avr utils is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with spreadspace avr utils. If not, see <http://www.gnu.org/licenses/>. + */ + +#include <avr/interrupt.h> +#include <avr/io.h> +#include <util/delay.h> + +#include "util.h" + +#if defined(CLKPR) +#define CPU_PRESCALE(n) do { CLKPR = 0x80; CLKPR = (n); } while(0) +#else +#define CPU_PRESCALE(n) +#endif + +void cpu_init(void) +{ + CPU_PRESCALE(0); +} + +#if defined JTD +void jtag_disable(void) +{ + uint8_t tempreg; + __asm __volatile("in %[tempreg], %[mcucr]" "\n\t" + "ori %[tempreg], %[jtd]" "\n\t" + "out %[mcucr], %[tempreg]" "\n\t" + "out %[mcucr], %[tempreg]" + : [tempreg] "=d" (tempreg) + : [mcucr] "I" (_SFR_IO_ADDR(MCUCR)), [jtd] "M" (_BV(JTD))); +} +#endif + +#if defined(__BOARD_teensy1__) + #define BOOTLOADER_VEC 0x3E00 +#elif defined(__BOARD_teensy2__) + #define BOOTLOADER_VEC 0x7E00 +#elif defined(__BOARD_teensy1pp__) + #define BOOTLOADER_VEC 0xFC00 +#elif defined(__BOARD_teensy2pp__) + #define BOOTLOADER_VEC 0x1FC00 +#elif defined(__BOARD_minimus__) + #define BOOTLOADER_VEC 0x3000 +#elif defined(__BOARD_minimus32__) + #define BOOTLOADER_VEC 0x3800 +#elif defined(__BOARD_hhd70dongle__) || defined(__BOARD_rda1846dongle__) || defined(__BOARD_culV3__) + #define BOOTLOADER_VEC 0x3800 +#elif defined(__BOARD_slowpandongle1__) || defined(__BOARD_slowpandongle2__) || defined(__BOARD_teenstep__) + #define BOOTLOADER_VEC 0x3800 +#else + #define BOOTLOADER_VEC 0x0000 +#endif + +typedef void (*f_ptr_type)(void); +f_ptr_type start_bootloader = (f_ptr_type)BOOTLOADER_VEC; + +void reset2bootloader(void) +{ +#if defined(__BOARD_teensy1__) || defined(__BOARD_teensy1pp__) || defined(__BOARD_teensy2__) || defined(__BOARD_teensy2pp__) || \ + defined(__BOARD_hhd70dongle__) || defined(__BOARD_rda1846dongle__) || defined(__BOARD_culV3__) || \ + defined(__BOARD_slowpandongle1__) || defined(__BOARD_slowpandongle2__) || defined(__BOARD_teenstep__) || \ + defined(__BOARD_minimus__) || defined(__BOARD_minimus32__) + cli(); + // disable watchdog, if enabled + // disable all peripherals + UDCON = 1; + USBCON = (1<<FRZCLK); // disable USB + UCSR1B = 0; + _delay_ms(5); + #if defined(__BOARD_teensy1__) + EIMSK = 0; PCICR = 0; SPCR = 0; ACSR = 0; EECR = 0; + TIMSK0 = 0; TIMSK1 = 0; UCSR1B = 0; + DDRB = 0; DDRC = 0; DDRD = 0; + PORTB = 0; PORTC = 0; PORTD = 0; + #elif defined(__BOARD_teensy2__) + EIMSK = 0; PCICR = 0; SPCR = 0; ACSR = 0; EECR = 0; ADCSRA = 0; + TIMSK0 = 0; TIMSK1 = 0; TIMSK3 = 0; TIMSK4 = 0; UCSR1B = 0; TWCR = 0; + DDRB = 0; DDRC = 0; DDRD = 0; DDRE = 0; DDRF = 0; TWCR = 0; + PORTB = 0; PORTC = 0; PORTD = 0; PORTE = 0; PORTF = 0; + #elif defined(__BOARD_teensy1pp__) + EIMSK = 0; PCICR = 0; SPCR = 0; ACSR = 0; EECR = 0; ADCSRA = 0; + TIMSK0 = 0; TIMSK1 = 0; TIMSK2 = 0; TIMSK3 = 0; UCSR1B = 0; TWCR = 0; + DDRA = 0; DDRB = 0; DDRC = 0; DDRD = 0; DDRE = 0; DDRF = 0; + PORTA = 0; PORTB = 0; PORTC = 0; PORTD = 0; PORTE = 0; PORTF = 0; + #elif defined(__BOARD_teensy2pp__) + EIMSK = 0; PCICR = 0; SPCR = 0; ACSR = 0; EECR = 0; ADCSRA = 0; + TIMSK0 = 0; TIMSK1 = 0; TIMSK2 = 0; TIMSK3 = 0; UCSR1B = 0; TWCR = 0; + DDRA = 0; DDRB = 0; DDRC = 0; DDRD = 0; DDRE = 0; DDRF = 0; + PORTA = 0; PORTB = 0; PORTC = 0; PORTD = 0; PORTE = 0; PORTF = 0; + #elif defined(__BOARD_minimus__) || defined(__BOARD_slowpandongle1__) + EIMSK = 0; PCICR = 0; SPCR = 0; ACSR = 0; EECR = 0; + TIMSK0 = 0; TIMSK1 = 0; UCSR1B = 0; + DDRB = 0; DDRC = 0; DDRD = 0; + PORTB = 0; PORTC = 0; PORTD = 0; + #elif defined(__BOARD_minimus32__) + EIMSK = 0; PCICR = 0; SPCR = 0; ACSR = 0; EECR = 0; + TIMSK0 = 0; TIMSK1 = 0; UCSR1B = 0; + DDRB = 0; DDRC = 0; DDRD = 0; + PORTB = 0; PORTC = 0; PORTD = 0; + #elif defined(__BOARD_hhd70dongle2__) || defined(__BOARD_hhd70dongle__) || defined(__BOARD_rda1846dongle__) || defined(__BOARD_culV3__) || \ + defined(__BOARD_slowpandongle2__) || defined(__BOARD_teenstep__) + EIMSK = 0; PCICR = 0; SPCR = 0; ACSR = 0; EECR = 0; ADCSRA = 0; + TIMSK0 = 0; TIMSK1 = 0; TIMSK3 = 0; TIMSK4 = 0; UCSR1B = 0; TWCR = 0; + DDRB = 0; DDRC = 0; DDRD = 0; DDRE = 0; DDRF = 0; TWCR = 0; + PORTB = 0; PORTC = 0; PORTD = 0; PORTE = 0; PORTF = 0; + #endif + start_bootloader(); +#endif +} |