diff options
| author | Christian Pointner <equinox@helsinki.at> | 2024-05-10 18:52:23 (GMT) |
|---|---|---|
| committer | Christian Pointner <equinox@helsinki.at> | 2024-05-10 18:52:23 (GMT) |
| commit | a641800acf13b5fb1463d4280c3ee7fc267143fb (patch) | |
| tree | 248b647a682f71d9eb90d14d24081368ea905a42 /snd-alpx/alpx_reg.h | |
| parent | cc4badffe0e02d159c21eb90ea080a6a2f90cb4b (diff) | |
import whole driver package
Diffstat (limited to 'snd-alpx/alpx_reg.h')
| -rw-r--r-- | snd-alpx/alpx_reg.h | 619 |
1 files changed, 0 insertions, 619 deletions
diff --git a/snd-alpx/alpx_reg.h b/snd-alpx/alpx_reg.h deleted file mode 100644 index 276e16d..0000000 --- a/snd-alpx/alpx_reg.h +++ /dev/null @@ -1,619 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* -* Support for Digigram AlpX PCI-e boards -* -* Copyright (c) 2024 Digigram Digital (info@digigram.com) -*/ - -#ifndef _ALPX_REG_H_ -#define _ALPX_REG_H_ - -/* Macros */ - -#define ALPX_BASE(variant, group) \ - (variant ## _ ## group ## _BASE) - -#define ALPX_OFFSET(variant, group, reg) \ - ((variant ## _ ## group ## _BASE) + \ - (variant ## _ ## group ## _ ## reg ## _REG)) - -#define ALPX_AREA(alpx_dev, variant, group) \ - ((alpx_dev)->base + ALPX_BASE(variant, group)) - -#define ALPX_ITEM_REG(variant, group, index) \ - ((variant ## _ ## group ## _BASE) + \ - (variant ## _ ## group ## _ ## index)) - -#define ALPX_REG(alpx_dev, variant, group, reg) \ - ((alpx_dev)->base + ALPX_OFFSET(variant, group, reg)) - -#define ALPX_REG_ARRAY(alpx_dev, variant, group, index) \ - ((alpx_dev)->base + ALPX_ITEM_REG(variant, group, index)) - -#define ALPX_COMMON_OFFSET(variant, group, reg) \ - ((variant ## _ ## group ## _BASE) + \ - (ALPX_COMMON_ ## reg ## _REG)) - -#define ALPX_COMMON_REG(alpx_dev, variant, group, reg) \ - ((alpx_dev)->base + ALPX_COMMON_OFFSET(variant, group, reg)) - -/* Conversion Register index to register offset, register are 32 bits words */ -#define ALP_INDEX_TO_REG_OFFSET(i) ((i) * 4) - - -/* PCI */ - -#define ALPX_PCI_BAR 0 -#define ALPX_PCI_ID_DEVICE 0x0002 - -#define ALPX_PCI_ID_SUBSYSTEM_MADI 0x0020 -#define ALPX_PCI_ID_SUBSYSTEM_ALP222 0x0040 -#define ALPX_PCI_ID_SUBSYSTEM_ALP222_MIC 0x0840 -#define ALPX_PCI_ID_SUBSYSTEM_ALP442 0x0080 -#define ALPX_PCI_ID_SUBSYSTEM_ALP442_MIC 0x0880 -#define ALPX_PCI_ID_SUBSYSTEM_ALP882 0x00C0 -#define ALPX_PCI_ID_SUBSYSTEM_ALP882_MIC 0x08C0 -#define ALPX_PCI_ID_SUBSYSTEM_MADI_LOOPBACK 0x0000 -#define ALPX_PCI_ID_SUBSYSTEM_ALPDANTE 0x00E0 - - -/* This one is a very special one : The production area is invalid */ -#define ALPX_PCI_ID_SUBSYSTEM_MADI_ALP_DEAD 0xDEAD - -/* UNKNOWN */ -#define ALPUNKNOWN_GPIO_BASE 0xFFFFF - -/* ALPX Base */ - -#define ALP_SHARED_BASE 0x50000 -#define ALP_SHARED_SIZE 8 * 1024 -#define ALP_PROC_BASE 0x60000 -#define ALP_CONTROL_BASE 0x70000 -#define ALP_CLK_MANAGER_BASE ALP_CONTROL_BASE - - -/* Alpxxx Flash defs */ -/** Common size for all the data areas in Flash, exclude the FIRMWARE **/ -#define ALPxxx_FLASH_DATA_AREAS_SIZE (32*1024) - -/** PRODUCTION Area in GOLDEN Region **/ -#define ALPxxx_FLASH_GOLDEN_PRODUCTION_BASE 0x228000 - -/* PRODUCTION structure */ -#define ALPX_SERIAL_OFFSET_IN_PRODUCTION 0 - -/* BUILD version register : common addresses */ -#define ALP_CONTROL_DESIGN_VERSION_REG 0x100 -#define ALP_CONTROL_BUILD_VERSION_REG 0x104 - -#define ALP_CONTROL_BUILD_VERSION_MASK GENMASK(15,0) - - -/** Multi-channels cards **/ - -/* Clock Manager */ -#define ALPMC_CLK_MANAGER_CONFIG_REG 0x24 -#define ALPMC_CLK_MANAGER_CONFIG_FS(v) ((v) & GENMASK(4, 0)) -#define ALPMC_CLK_MANAGER_CONFIG_FS_MASK GENMASK(4, 0) - - -#define ALPMC_CLK_MANAGER_EFFECTIVE_FS(v) (((v) & GENMASK(20, 16)) >> 16) -#define ALPMC_CLK_MANAGER_EFFECTIVE_FS_INVALID 0 -#define ALPMC_CLK_MANAGER_EFFECTIVE_FS_32K 5 -#define ALPMC_CLK_MANAGER_EFFECTIVE_FS_44_1K 6 -#define ALPMC_CLK_MANAGER_EFFECTIVE_FS_48K 7 -#define ALPMC_CLK_MANAGER_EFFECTIVE_FS_DOUBLE BIT(3) -#define ALPMC_CLK_MANAGER_EFFECTIVE_FS_QUAD BIT(4) -#define ALPMC_CLK_MANAGER_EFFECTIVE_FS_BASE_MASK GENMASK(2, 0) - - -#define ALPMC_CLK_MANAGER_CONFIG_CLK_CURRENT_VALUE_MASK GENMASK(20, 16) -#define ALPMC_CLK_MANAGER_CONFIG_CLK_CURRENT_VALUE_POS 16 -#define ALPMC_CLK_MANAGER_CONFIG_CLK_CURRENT_VALUE_QTY 8 - -#define ALPMC_CLK_MANAGER_SOURCE(v) (((v) & GENMASK(23, 21)) >> 21) -#define ALPMC_CLK_MANAGER_SOURCE_INTERNAL 0 -#define ALPMC_CLK_MANAGER_SOURCE_SIC 1 -#define ALPMC_CLK_MANAGER_SOURCE_WCLK_IN 2 -#define ALPMC_CLK_MANAGER_SOURCE_AES_SYNC 3 -#define ALPMC_CLK_MANAGER_SOURCE_AES_AUDIO_12 4 -#define ALPMC_CLK_MANAGER_SOURCE_AES_AUDIO_34 5 -#define ALPMC_CLK_MANAGER_SOURCE_AES_AUDIO_56 6 -#define ALPMC_CLK_MANAGER_SOURCE_AES_AUDIO_78 7 -#define ALPMC_CLK_MANAGER_SOURCE_DANTE 8 - -/* Pre FW V240 compatibility support */ -#define ALP882_APP_PREFW240_CLK_MANAGER_SOURCE_WCLK_IN 0 -#define ALP882_APP_PREFW240_CLK_MANAGER_SOURCE_AES_SYNC 1 -#define ALP882_APP_PREFW240_CLK_MANAGER_SOURCE_AES_AUDIO_12 2 -#define ALP882_APP_PREFW240_CLK_MANAGER_SOURCE_AES_AUDIO_34 3 -#define ALP882_APP_PREFW240_CLK_MANAGER_SOURCE_AES_AUDIO_56 4 -#define ALP882_APP_PREFW240_CLK_MANAGER_SOURCE_AES_AUDIO_78 5 -#define ALP882_APP_PREFW240_CLK_MANAGER_SOURCE_INTERNAL 6 - -#define ALPMC_CLK_MANAGER_CONFIG_CLK_SRC_MASK GENMASK(23, 21) -#define ALPMC_CLK_MANAGER_CONFIG_CLK_SRC_POS 21 - -#define ALPMC_CLK_MANAGER_BASE ALP_CLK_MANAGER_BASE -#define ALPMC_CONTROL_BASE ALP_CLK_MANAGER_BASE -#define ALPMC_GPIO_BASE 0x45000 -#define ALPMC_CODEC_CTRL_BASE 0x71000 -#define ALPMC_MIXER_BASE 0x74000 -#define ALPMC_AMPLI_IN_BASE 0x79000 -#define ALPMC_AMPLI_OUT_BASE 0x7c000 - -/* FS switch delay required by HW (in ms) */ -#define ALPMC_FS_SWITCH_DELAY 500 - -/* Supported Firmware versions */ -#define ALPMC_SUPPORTED_BASE_FW_VERSION 247 -#define ALP222_SUPPORTED_BASE_FW_VERSION 283 -/* The base Firmware version for AlpDANTE supported by this driver */ -#define ALPDANTE_SUPPORTED_BASE_FW_VERSION 316 - - - -/* GPIO */ - -#define ALPMC_GPIO_INPUT_REG 0x08 -#define ALPMC_GPIO_INPUT_QTY 8 -#define ALPMC_GPIO_OUTPUT_REG 0x0C -#define ALPMC_GPIO_OUTPUT_QTY 8 - -/* ALPMC Gain access*/ -#define ALPMC_GAIN_TABLE_BASE(c) (0xc + (c) * 0x4) - -/* Codec */ -#define ALPMC_INPUT_PARAMS_REG 0x2C -#define ALPMC_MIC_INPUT_PH_1_MASK BIT(0) -#define ALPMC_MIC_INPUT_PH_2_MASK BIT(1) -#define ALPMC_MIC_INPUT_PH_3_MASK BIT(2) -#define ALPMC_MIC_INPUT_PH_4_MASK BIT(3) -#define ALPMC_MIC_INPUT_PH_5_MASK BIT(4) -#define ALPMC_MIC_INPUT_PH_6_MASK BIT(5) -#define ALPMC_MIC_INPUT_PH_7_MASK BIT(6) -#define ALPMC_MIC_INPUT_PH_8_MASK BIT(7) - -#define ALPMC_MIC_INPUT_PH_1_POS 0 -#define ALPMC_MIC_INPUT_PH_2_POS 1 -#define ALPMC_MIC_INPUT_PH_3_POS 2 -#define ALPMC_MIC_INPUT_PH_4_POS 3 -#define ALPMC_MIC_INPUT_PH_5_POS 4 -#define ALPMC_MIC_INPUT_PH_6_POS 5 -#define ALPMC_MIC_INPUT_PH_7_POS 6 -#define ALPMC_MIC_INPUT_PH_8_POS 7 - -#define ALPMC_CODEC_PGA_REGS 0x0C - -#define ALPMC_CODEC_AES_SRC_CONTROL_REG 0x08 -#define ALPMC_CODEC_AES_SRC_CONTROL_AUTO_DISABLE_1_2 BIT(0) -#define ALPMC_CODEC_AES_SRC_CONTROL_AUTO_DISABLE_3_4 BIT(1) -#define ALPMC_CODEC_AES_SRC_CONTROL_AUTO_DISABLE_5_6 BIT(2) -#define ALPMC_CODEC_AES_SRC_CONTROL_AUTO_DISABLE_7_8 BIT(3) - -#define ALPMC_CODEC_AES_SRC_1_2_MASK BIT(0) -#define ALPMC_CODEC_AES_SRC_1_2_POS 0 -#define ALPMC_CODEC_AES_SRC_3_4_MASK BIT(1) -#define ALPMC_CODEC_AES_SRC_3_4_POS 1 -#define ALPMC_CODEC_AES_SRC_5_6_MASK BIT(2) -#define ALPMC_CODEC_AES_SRC_5_6_POS 2 -#define ALPMC_CODEC_AES_SRC_7_8_MASK BIT(3) -#define ALPMC_CODEC_AES_SRC_7_8_POS 3 - -/* MC Mixer */ -/* One Gain value per register */ -#define ALPMC_MIXER_ENTRIES_IN_REG 1 - -#define ALPMC_MIXER_GAIN_MASK GENMASK(ALPX_MIXER_GAIN_BITS - 1, 0) - -#define ALPMC_MIXER_GAIN_SEL(v) ((v) & GENMASK(ALPX_MIXER_GAIN_BITS - 1, 0)) - -#define ALPMC_MIXER_GAIN_VALUE(v) ((v) & GENMASK(ALPX_MIXER_GAIN_BITS-1, 0)) - -#define ALPMC_MIXER_GAIN_REG(size, in, out) (ALPX_MIXER_REG_ENTRIES_OFFSET + (out) * ((size) * 4 / ALPMC_MIXER_ENTRIES_IN_REG) + ((in) / ALPMC_MIXER_ENTRIES_IN_REG) * 4) - - -/* Dedicated to ALP882 */ - -#define ALP882_CHANNELS_DAW_COUNT 16 -#define ALP882_CHANNELS_ANALOG_COUNT 8 -#define ALP882_CHANNELS_AES_COUNT 8 - -#define ALP882_CHANNELS_IN_DAW_OFFSET 0 -#define ALP882_CHANNELS_IN_ANALOG_OFFSET (ALP882_CHANNELS_IN_DAW_OFFSET + \ - ALP882_CHANNELS_DAW_COUNT) -#define ALP882_CHANNELS_IN_AES_OFFSET (ALP882_CHANNELS_IN_ANALOG_OFFSET + \ - ALP882_CHANNELS_ANALOG_COUNT) - -#define ALP882_CHANNELS_OUT_ANALOG_OFFSET 0 -#define ALP882_CHANNELS_OUT_AES_OFFSET (ALP882_CHANNELS_OUT_ANALOG_OFFSET + \ - ALP882_CHANNELS_ANALOG_COUNT) -#define ALP882_CHANNELS_OUT_DAW_OFFSET (ALP882_CHANNELS_OUT_AES_OFFSET + \ - ALP882_CHANNELS_AES_COUNT) - - -/* ALP882 Clock Manager */ -#define ALP882_CLK_MANAGER_CONFIG_CLK_SRC_QTY 8 - -/* Alp 882 clk source in Pre 240 FW */ -#define ALP882_APP_PREFW240_CLK_MANAGER_CLK_SRC_QTY 7 - -/* Mixer 882 */ -#define ALP882_MIXER_SIZE 32 - -/* Dedicated to ALP442 */ - -#define ALP442_CHANNELS_ANALOG_COUNT 4 -#define ALP442_CHANNELS_AES_COUNT 4 -#define ALP442_CHANNELS_DAW_COUNT (ALP442_CHANNELS_ANALOG_COUNT + \ - ALP442_CHANNELS_AES_COUNT) - - -#define ALP442_CHANNELS_IN_DAW_OFFSET 0 -#define ALP442_CHANNELS_IN_ANALOG_OFFSET (ALP442_CHANNELS_IN_DAW_OFFSET + \ - ALP442_CHANNELS_DAW_COUNT) -#define ALP442_CHANNELS_IN_AES_OFFSET (ALP442_CHANNELS_IN_ANALOG_OFFSET + \ - ALP442_CHANNELS_ANALOG_COUNT) - -#define ALP442_CHANNELS_OUT_ANALOG_OFFSET 0 -#define ALP442_CHANNELS_OUT_AES_OFFSET (ALP442_CHANNELS_OUT_ANALOG_OFFSET + \ - ALP442_CHANNELS_ANALOG_COUNT) -#define ALP442_CHANNELS_OUT_DAW_OFFSET (ALP442_CHANNELS_OUT_AES_OFFSET + \ - ALP442_CHANNELS_AES_COUNT) - - -/* ALP442 Clock Manager */ -#define ALP442_CLK_MANAGER_CONFIG_CLK_SRC_QTY 6 -#define ALP442_CLK_MANAGER_SOURCE_INTERNAL ALPMC_CLK_MANAGER_SOURCE_INTERNAL - -/* Mixer 442 */ -#define ALP442_MIXER_SIZE (ALP442_CHANNELS_ANALOG_COUNT + \ - ALP442_CHANNELS_AES_COUNT + \ - ALP442_CHANNELS_DAW_COUNT) - - - -/* Alp 222 */ - -#define ALP222_ANALOG_QTY 0x2 -#define ALP222_AES3_QTY 0x2 - -#define ALP222_EXT_CHANNEL_QTY (ALP222_ANALOG_QTY + ALP222_AES3_QTY) - -#define ALP222_DAW_QTY ALP222_EXT_CHANNEL_QTY - - -#define ALP222_CLK_MANAGER_BASE ALP_CLK_MANAGER_BASE -#define ALP222_CONTROL_BASE ALP_CLK_MANAGER_BASE -#define ALP222_AMPLI_IN_BASE 0x79000 -#define ALP222_AMPLI_OUT_BASE 0x7c000 -#define ALP222_CODEC_CTRL_BASE 0x71000 -#define ALP222_GPIO_BASE 0x45000 -#define ALP222_MIXER_BASE 0x73000 - -#define ALP222_DAW_PLAYBACK_AMPLI_BASE ALP222_AMPLI_IN_BASE + ALPX_GAIN_REG(0) -#define ALP222_ANALOG_CAPTURE_AMPLI_BASE ALP222_AMPLI_IN_BASE + ALPX_GAIN_REG(ALP222_DAW_QTY) -#define ALP222_AES3_CAPTURE_AMPLI_BASE ALP222_AMPLI_IN_BASE + ALPX_GAIN_REG(ALP222_DAW_QTY + ALP222_ANALOG_QTY) - -#define ALP222_ANALOG_PLAYBACK_AMPLI_BASE ALP222_AMPLI_OUT_BASE + ALPX_GAIN_REG(0) -#define ALP222_AES3_PLAYBACK_AMPLI_BASE ALP222_AMPLI_OUT_BASE + ALPX_GAIN_REG(ALP222_ANALOG_QTY) -#define ALP222_DAW_CAPTURE_AMPLI_BASE ALP222_AMPLI_OUT_BASE + ALPX_GAIN_REG(ALP222_ANALOG_QTY + ALP222_AES3_QTY) - - -/* Alp222 GPIO */ -#define ALP222_GPIO_INPUT_REG 0x00 -#define ALP222_GPIO_INPUT_QTY 2 -#define ALP222_GPIO_OUTPUT_REG 0x08 -#define ALP222_GPIO_OUTPUT_QTY 2 - -/* Alp222 CODEC*/ -#define ALP222_CODEC_PGA_REGS 0x08 - -/* Alp MADI */ -#define ALP222_MADI_QTY 0x40 - -#define ALPMADI_CHANNEL_QTY ALP222_MADI_QTY - -//MADI Unit & DAW Unit -#define ALPMADI_AUDIO_UNIT_QTY 2 - -#define ALPMADI_CLK_MANAGER_BASE ALP_CLK_MANAGER_BASE -#define ALPMADI_CONTROL_BASE ALP_CLK_MANAGER_BASE -#define ALPMADI_ROUTER_IN_BASE 0x71000 -#define ALPMADI_MIXER_BASE 0x72000 -#define ALPMADI_ROUTER_OUT_BASE 0x73000 -#define ALPMADI_MEAS_DAW_IN_BASE 0x74000 -#define ALPMADI_GAIN_DAW_IN_BASE 0x75000 -#define ALPMADI_MEAS_DAW_OUT_BASE 0x76000 -#define ALPMADI_GAIN_DAW_OUT_BASE 0x77000 -#define ALPMADI_MEAS_MADI_IN_BASE 0x78000 -#define ALPMADI_GAIN_MADI_IN_BASE 0x79000 -#define ALPMADI_MEAS_MADI_OUT_BASE 0x7A000 -#define ALPMADI_GAIN_MADI_OUT_BASE 0x7B000 -#define ALPMADI_GPIO_BASE ALPUNKNOWN_GPIO_BASE - -#define ALPMADI_GPIO_INPUT_REG 0xFF -#define ALPMADI_GPIO_OUTPUT_REG 0xFF - -/* Common */ - -#define ALPX_COMMON_ID_REG 0x0 - - -#define ALPX_COMMON_VERSION_REG 0x4 -#define ALPX_COMMON_VERSION_VERSION(v) ((v) >> 16) -#define ALPX_COMMON_VERSION_REVISION(v) ((v) & GENMASK(15, 0)) - -#define ALPX_DANTE_VERSION_VERSION(v) ((v) >> 8) -#define ALPX_DANTE_VERSION_REVISION(v) ((v) & GENMASK(7, 0)) - - -/* Common Clock 222/882 models*/ - -#define ALPxxx_CLK_MANAGER_CLK_VALUES_QTY 14 - -/* Values below use the full 5 bits of clock definitions : factor | base */ -#define ALPxxx_CLK_MANAGER_CLK_VALUE_8K (0) -#define ALPxxx_CLK_MANAGER_CLK_VALUE_11_025K (1) -#define ALPxxx_CLK_MANAGER_CLK_VALUE_16K (2) -#define ALPxxx_CLK_MANAGER_CLK_VALUE_22_05K (3) -#define ALPxxx_CLK_MANAGER_CLK_VALUE_24K (4) -#define ALPxxx_CLK_MANAGER_CLK_VALUE_32K (5) -#define ALPxxx_CLK_MANAGER_CLK_VALUE_44_1K (6) -#define ALPxxx_CLK_MANAGER_CLK_VALUE_48K (7) -#define ALPxxx_CLK_MANAGER_CLK_VALUE_64K (0xD) -#define ALPxxx_CLK_MANAGER_CLK_VALUE_128K (0x15) -#define ALPxxx_CLK_MANAGER_CLK_VALUE_88_2K (0xE) -#define ALPxxx_CLK_MANAGER_CLK_VALUE_176_4K (0x16) -#define ALPxxx_CLK_MANAGER_CLK_VALUE_96K (0xF) -#define ALPxxx_CLK_MANAGER_CLK_VALUE_192K (0x17) - -/* ALP222 Clock Manager */ - -#define ALP222_CLK_MANAGER_CONFIG_REG 0x28 -#define ALP222_CLK_MANAGER_CONFIG_FS_MASK GENMASK(4, 0) -#define ALP222_CLK_MANAGER_CONFIG_CLK_CURRENT_VALUE_MASK GENMASK(20, 16) -#define ALP222_CLK_MANAGER_CONFIG_CLK_CURRENT_VALUE_POS 16 - - -#define ALP222_CLK_MANAGER_CLK_SRC_MASK GENMASK(23, 21) -#define ALP222_CLK_MANAGER_CLK_SRC_POS 21 -#define ALP222_CLK_MANAGER_CLK_SRC_QTY 5 -#define ALP222_CLK_MANAGER_CLK_SRC_INTERNAL (0) -#define ALP222_CLK_MANAGER_CLK_SRC_SIC (1) -#define ALP222_CLK_MANAGER_CLK_SRC_WCLK (2) -#define ALP222_CLK_MANAGER_CLK_SRC_AES_SYNC (3) -#define ALP222_CLK_MANAGER_CLK_SRC_AES_AUDIO (4) -#define ALP222_CLK_MANAGER_CLK_SRC_MAX ALP222_CLK_MANAGER_CLK_SRC_AES_AUDIO - -/* Pre FW 283 clock sources definitions */ -#define ALP222_APPS_PREFW283_CLK_MANAGER_CLK_SRC_QTY 4 -#define ALP222_CLK_MANAGER_APPSPREFW283_CLK_SRC_WCLK 0 -#define ALP222_CLK_MANAGER_APPSPREFW283_CLK_SRC_AES_SYNC 1 -#define ALP222_CLK_MANAGER_APPSPREFW283_CLK_SRC_AES_AUDIO 2 -#define ALP222_CLK_MANAGER_APPSPREFW283_CLK_SRC_INTERNAL 3 - -/* ALPMADI Clock Manager */ - -#define ALPMADI_CLK_MANAGER_CONFIG_REG 0x1C -#define ALPMADI_CLK_MANAGER_CONFIG_FS_MASK GENMASK(10, 8) -#define ALPMADI_CLK_MANAGER_CONFIG_FS_44_1K (0 << 8) -#define ALPMADI_CLK_MANAGER_CONFIG_FS_48K (1 << 8) -#define ALPMADI_CLK_MANAGER_CONFIG_FS_88_2K (2 << 8) -#define ALPMADI_CLK_MANAGER_CONFIG_FS_96K (3 << 8) -#define ALPMADI_CLK_MANAGER_CONFIG_FS_176_4K (4 << 8) -#define ALPMADI_CLK_MANAGER_CONFIG_FS_192K (5 << 8) - -/* AlpDANTE Clock Manager clock registervalues*/ -#define ALPDANTE_CLK_MANAGER_CLK_VALUE_44_1K 0x01 -#define ALPDANTE_CLK_MANAGER_CLK_VALUE_48K 0x00 -#define ALPDANTE_CLK_MANAGER_CLK_VALUE_88_2K 0x03 -#define ALPDANTE_CLK_MANAGER_CLK_VALUE_96K 0x02 -#define ALPDANTE_CLK_MANAGER_CLK_VALUE_176_4K 0x05 -#define ALPDANTE_CLK_MANAGER_CLK_VALUE_192K 0x04 - -/* ALPX PROC */ -/* Embedded processor dedicated area length (in bytes) */ -#define ALP_PROC_AREA_LENGTH 0x800U - -#define ALP_PROC_VERSION_REG 0x00 - -#define ALP_PROC_STATUS_REG 0x04 -#define ALP_PROC_STATUS_FAIL BIT(0) -#define ALP_PROC_STATUS_PENDING BIT(1) - -#define ALP_PROC_FAILS_REG 0x08 -#define ALP_PROC_FAILS_FAIL_NONE 0 - -#define ALP_PROC_COMMAND_REG 0x0C - -#define ALP_PROC_COMMAND_MAKE_P16(_cmd, _p16) ((((_p16) & 0x0FFFF) << 8) | \ - (_cmd)) -#define ALP_PROC_CMD_READ_FLASH_SECTOR 0x10 -#define ALP_PROC_CMD_WRITE_FLASH_SECTOR 0x0A - -#define ALP_PROC_FWCONFIG_REG 0x10 -#define ALP_PROC_FWCONFIG_CLKSRC_UP_MASK GENMASK(0,0) -#define ALP_PROC_FWCONFIG_CLKSRC_UP_POS 0 - -#define ALP_PROC_FWCONFIG_CLKSRC_DOWN_MASK GENMASK(1,1) -#define ALP_PROC_FWCONFIG_CLKSRC_DOWN_POS 1 - - -/* PROC Logs base register */ -#define ALP_PROC_LOG_OFFSET 0x40U -#define ALP_PROC_LOG_BASE ALP_PROC_BASE + ALP_PROC_LOG_OFFSET - -/* Log length, -8 ?? but done in the reference application from Easii-IC (log.c) */ -#define ALP_PROC_LOG_LENGTH ALP_PROC_AREA_LENGTH - ALP_PROC_LOG_OFFSET - 8U - -/* Clock source priority def */ -#define ALP_PROC_CLK_SOURCE_PRIO_REG 0x14 - -#define ALP_PROC_CLK_SOURCE_PRIO0_MASK GENMASK(3,0) -#define ALP_PROC_CLK_SOURCE_PRIO0_POS 0 - -#define ALP_PROC_CLK_SOURCE_PRIO1_MASK GENMASK(7,4) -#define ALP_PROC_CLK_SOURCE_PRIO1_POS 4 - -#define ALP_PROC_CLK_SOURCE_PRIO2_MASK GENMASK(11,8) -#define ALP_PROC_CLK_SOURCE_PRIO2_POS 8 - -#define ALP_PROC_CLK_SOURCE_PRIO3_MASK GENMASK(15,12) -#define ALP_PROC_CLK_SOURCE_PRIO3_POS 12 - -/* ALPX GPIO */ -#define ALPX_GPIO_MASK(i) BIT(i) -#define ALPX_GPIO_SEL(i, v) (((v) << (i)) & ALPX_GPIO_MASK(i)) -#define ALPX_GPIO_VALUE(i, v) (((v) & ALPX_GPIO_MASK(i)) >> (i)) - -/* Control */ -#define ALP_CONTROL_PCIE_SUBSYS_ID_REG 0x8 -#define ALP_CONTROL_SAMPLES_CNT_REG 0x18 -#define ALP_CLK_MANAGER_SAMPLES_COUNT_REG 0x18 - -#define ALP222_CONTROL_PCIE_MASK_IT_REG 0xc -#define ALP222_CONTROL_WC_RTERM_REG 0x1c -#define ALP222_CONTROL_PCIE_WARM_RESET_REG 0x10 -#define ALP222_CONTROL_PCIE_WARM_RESET_VALUE 0xc07d8e51 -#define ALP222_CONTROL_PCIE_COLD_RESET_REG 0x14 -#define ALP222_CONTROL_PCIE_COLD_RESET_VALUE 0x8e5ef96a -#define ALP222_CONTROL_FS_REG 0x28 -#define ALP222_CODEC_CTRL_ASRC_REG 0x10 -#define ALP222_MIC_CONTROL_REG 0x24 - -#define ALPMADI_CONTROL_WARM_REBOOT_FPGA_REG 0x10 -#define ALPMADI_CONTROL_COLD_REBOOT_FPGA_REG 0x14 -#define ALPMADI_CONTROL_BLINK_LED_REG 0x20 -#define ALPMADI_CONTROL_EXT_ITF_CONFIG_REG 0x24 -#define ALPMADI_CONTROL_FS_SEL_REG 0x28 - -#define ALPMADI_CONTROL_EXT0_STATUS_CTRL_REG 0x2c -#define ALPMADI_CONTROL_EXT1_STATUS_CTRL_REG 0x30 -#define ALPMADI_CONTROL_EXT2_STATUS_CTRL_REG 0x34 -#define ALPMADI_CONTROL_EXT3_STATUS_CTRL_REG 0x38 -#define ALPMADI_CONTROL_PI_PARAMS_REG 0x3c - - -#define ALPMADI_CONTROL_BLINK_LED_EN BIT(0) -#define ALPMADI_CONTROL_PI_PARAMS_KI(v) ((v) & GENMASK(15, 0)) -#define ALPMADI_CONTROL_PI_PARAMS_KP(v) (((v) << 16) & GENMASK(31, 16)) -#define ALPMADI_CONTROL_EXT_ITF_CONFIG_MADI_LINK(v) ((v) & GENMASK(1, 0)) -#define ALPMADI_CONTROL_EXT_ITF_CONFIG_BNC_SIGNAL(v) (((v<<8)) & GENMASK(8, 8)) - -/* Codec */ -#define ALPX_CODEC_CTRL_GAIN_REG(i) ((i) * 0x4) - -/* Gains */ -#define ALPX_GAIN_VALUE_BITS 10 -#define ALPX_GAIN_REG_ENTRIES_OFFSET 0xC -#define ALPX_GAIN_REG(i) (ALPX_GAIN_REG_ENTRIES_OFFSET + (i) * 0x4) - -/* Router */ -#define ALPMADI_ROUTER_SIZE 128 - -#define ALPX_ROUTER_REG_ENTRIES_OFFSET 0x8 - -/* RAW ACCESS to router register i*/ -#define ALPX_ROUTER_REG(i) (0x8 + ((i) / 4) * 0x4) - -#define ALPX_ROUTER_SHIFT(i) (((i) % 4) * 8) -#define ALPX_ROUTER_MASK(i) (GENMASK(7, 0) << \ - ALPX_ROUTER_SHIFT(i)) -#define ALPX_ROUTER_SEL(i, v) (((v) & GENMASK(7, 0)) << \ - ALPX_ROUTER_SHIFT(i)) -#define ALPX_ROUTER_VALUE(i, v) (((v) >> \ - ALPX_ROUTER_SHIFT(i)) & \ - GENMASK(7, 0)) - -#define ALPMADI_ROUTER_PORT(i) (ALPX_ROUTER_REG_ENTRIES_OFFSET + ((i) * 0x4)) - -#define ALPMADI_ROUTER_IN_PORT(i) ALPMADI_ROUTER_PORT(i) - -#define ALPMADI_ROUTER_OUT_PORT(i) ALPMADI_ROUTER_PORT(i) - -/* Mixer */ -#define ALPX_MIXER_GAIN_BITS 10 -#define ALPX_GAIN_0dB 0x385 -#define ALPX_GAIN_MUTE 0x000 - -/** Mixer 222 **/ - -/* Mixer Input i, output j & j+1*/ -#define ALP222_MIXER_SIZE 8 -#define ALPMADI_MIXER_SIZE 16 - -//2 gains per register -#define ALPMADI_MIXER_BANK_SIZE 2 - -#define ALP222_MIXER_ENTRIES_IN_REG 2 - -//#define ALPX_GAIN_REG_VALUE_STEP_PER_DB 10 -#define ALPX_GAIN_dB_TO_10ofdB (dB) ((db) * 10) - - -#define ALPX_GAIN_REG_VALUE_FROM_10ofDB(val10ofdb) (ALPX_GAIN_0dB + (val10ofdb)) - -#define ALPX_MIXER_REG_ENTRIES_OFFSET 0x8 - -/* Return the @reg for the given (input/output) in the mixer. MIND the register structure !! */ -//MADI structured as In into Outs -//EDF MADI formula TO BE CHECKED -//#define ALPMADI_MIXER_GAIN_REG(mixerSize, inputId, outputId) (0x8 + ((((mixerSize) * (inputId) + (outputId)) * 4 / ALPX_MIXER_ENTRIES_IN_REG))) - -// Structured as : Out from Ins -#define ALP222_MIXER_GAIN_REG(size, in, out) (ALPX_MIXER_REG_ENTRIES_OFFSET + (out) * ((size) * 4 / ALP222_MIXER_ENTRIES_IN_REG) + ((in) / ALP222_MIXER_ENTRIES_IN_REG) * 4) - -//Odd entry is in higher bits -#define ALP222_MIXER_GAIN_SHIFT_STEP(i) (((i) & 1) ? ALPX_MIXER_GAIN_BITS : 0) - -#define ALP222_MIXER_GAIN_MASK(i) (GENMASK(ALPX_MIXER_GAIN_BITS-1, 0) << \ - ALP222_MIXER_GAIN_SHIFT_STEP(i)) - -#define ALP222_MIXER_GAIN_SEL(i, v) (((v) & GENMASK(ALPX_MIXER_GAIN_BITS-1, 0)) << \ - ALP222_MIXER_GAIN_SHIFT_STEP(i)) - -#define ALP222_MIXER_GAIN_VALUE(i, v) (((v) >> \ - ALP222_MIXER_GAIN_SHIFT_STEP(i)) & \ - GENMASK(ALPX_MIXER_GAIN_BITS-1, 0)) - - -//Build the mixer register -//#define ALP222_MIXER_REG_VALUE(left, right) ((left)<< ALP_GAIN_VALUE_BITS | (right)) - -// Flags access -#define ALP222_CODEC_CTRL_ASRC_MASK GENMASK(0, 0) -#define ALP222_CODEC_CTRL_ASRC_POS 0 - -// MIC Options defs -#define ALP222_MIC_GAIN_L_MASK GENMASK(7,0) -#define ALP222_MIC_GAIN_L_POS 0 -#define ALP222_MIC_GAIN_WIDTH 8 - -#define ALP222_MIC_GAIN_R_MASK GENMASK(15,8) -#define ALP222_MIC_GAIN_R_POS 8 - - -#define ALP222_MIC_DC_L_MASK GENMASK(16,16) -#define ALP222_MIC_DC_L_POS 16 -#define ALP222_MIC_CM_L_MASK GENMASK(17,17) -#define ALP222_MIC_CM_L_POS 17 -#define ALP222_MIC_PH_L_MASK GENMASK(18,18) -#define ALP222_MIC_PH_L_POS 18 - -#define ALP222_MIC_DC_R_MASK GENMASK(19,19) -#define ALP222_MIC_DC_R_POS 19 -#define ALP222_MIC_CM_R_MASK GENMASK(20,20) -#define ALP222_MIC_CM_R_POS 20 -#define ALP222_MIC_PH_R_MASK GENMASK(21,21) -#define ALP222_MIC_PH_R_POS 21 - -#define ALP222_MIC_EN_L_MASK GENMASK(22,22) -#define ALP222_MIC_EN_R_MASK GENMASK(23,23) -#define ALP222_MIC_EN_L_POS 22 -#define ALP222_MIC_EN_R_POS 23 - - -#define ALP222_MIC_HERE_POS 31 - -#endif |