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authorChristian Pointner <equinox@helsinki.at>2024-05-10 18:56:00 (GMT)
committerChristian Pointner <equinox@helsinki.at>2024-05-10 18:56:00 (GMT)
commitaf6bfbbd2496b1f5aa02b94caff4e6f988fa32c9 (patch)
tree45bebb68a0bf3bfc2fff1646f6fa0f4b976fba57 /snd-alpx-dkms/snd-alpx/alpx_axcmem.h
parent7035064ca063fdf15669ceb790ecef1e5ed054b0 (diff)
rename package to snd-alpx-dkms
Diffstat (limited to 'snd-alpx-dkms/snd-alpx/alpx_axcmem.h')
-rw-r--r--snd-alpx-dkms/snd-alpx/alpx_axcmem.h115
1 files changed, 115 insertions, 0 deletions
diff --git a/snd-alpx-dkms/snd-alpx/alpx_axcmem.h b/snd-alpx-dkms/snd-alpx/alpx_axcmem.h
new file mode 100644
index 0000000..20b35a0
--- /dev/null
+++ b/snd-alpx-dkms/snd-alpx/alpx_axcmem.h
@@ -0,0 +1,115 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+* Support for Digigram AlpX PCI-e boards
+*
+* Copyright (c) 2024 Digigram Digital (info@digigram.com)
+*/
+
+#ifndef _ALPX_AXCMEM_H_
+#define _ALPX_AXCMEM_H_
+
+#include "alpx.h"
+
+#include <linux/types.h>
+#include <linux/io.h>
+
+
+/** Types **/
+
+/* Register's location in AXCMEM area */
+struct alpx_axcmem_loc
+{
+ uint32_t page; /* page index, absolute or relative to a page group */
+ uint32_t line; /* line index */
+ uint32_t row; /* Row index */
+};
+
+/** Services **/
+/* Navigation */
+
+/* return the register's address given the alp device and register's location */
+void* alpx_axcmem_getRegAddr(struct alpx_device* alp,
+ const struct alpx_axcmem_loc* loc);
+
+/* Return the register's address in a pointed page through the given reference register's localation, base is the address of the used PCI BAR */
+void* alpx_axcmem_getPointedRegAddrByRefLoc(struct alpx_device* alp,
+ const struct alpx_axcmem_loc* ref_loc,
+ const struct alpx_axcmem_loc* loc);
+
+
+
+/* Values, these functions check the value alignement ! Use assertion !*/
+/* Values Little Endian by default, "BE" for big endian */
+static inline uint8_t alpx_axcmem_getRegU8Value(void* addr)
+{
+ return readb(addr);
+}
+
+static inline void alpx_axcmem_setRegU8Value(void* addr, uint8_t value)
+{
+ writeb(value, addr);
+}
+
+static inline uint16_t alpx_axcmem_getRegU16Value(void* addr)
+{
+ return le16_to_cpu(readw(addr));
+}
+
+static inline void alpx_axcmem_setRegU16Value(void* addr, uint16_t value)
+{
+ writew(cpu_to_le16(value), addr);
+}
+
+static inline uint16_t alpx_axcmem_getRegBEU16Value(void* addr)
+{
+ return be16_to_cpu(alpx_axcmem_getRegU16Value(addr));
+
+}
+
+static inline void alpx_axcmem_setRegBEU16Value(void* addr, uint16_t value)
+{
+ writew(cpu_to_be16(value), addr);
+}
+
+
+static inline uint32_t alpx_axcmem_getRegU32Value(void* addr)
+{
+ return le32_to_cpu(readl(addr));
+}
+
+static inline void alpx_axcmem_setRegU32Value(void* addr, uint32_t value)
+{
+
+ writel(cpu_to_le32(value), addr);
+}
+
+static inline uint32_t alpx_axcmem_getRegBEU32Value(void* addr)
+{
+ return be32_to_cpu(readl(addr));
+}
+
+static inline void alpx_axcmem_setRegBEU32Value(void* addr, uint32_t value)
+{
+
+ writel(cpu_to_be32(value), addr);
+}
+/* Same but can be used as ptr : not inlined*/
+uint32_t alpx_axcmem_getRegU8Value_ptr(void* addr);
+void alpx_axcmem_setRegU8Value_ptr(void* addr, uint32_t value);
+uint32_t alpx_axcmem_getRegU16Value_ptr(void* addr);
+void alpx_axcmem_setRegU16Value_ptr(void* addr, uint32_t value);
+uint32_t alpx_axcmem_getRegBEU16Value_ptr(void* addr);
+void alpx_axcmem_setRegBEU16Value_ptr(void* addr, uint32_t value);
+uint32_t alpx_axcmem_getRegU32Value_ptr(void* addr);
+void alpx_axcmem_setRegU32Value_ptr(void* addr, uint32_t value);
+uint32_t alpx_axcmem_getRegBEU32Value_ptr(void* addr);
+void alpx_axcmem_setRegBEU32Value_ptr(void* addr, uint32_t value);
+
+
+int alpx_acxmem_getByteArrayByRefLoc(struct alpx_device* alp,
+ const struct alpx_axcmem_loc* ref_loc,
+ const struct alpx_axcmem_loc* loc,
+ unsigned char* dst,
+ unsigned int length);
+
+#endif /*_ALPX_AXCMEM_H_*/