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authorChristian Pointner <equinox@spreadspace.org>2015-03-31 22:39:17 (GMT)
committerChristian Pointner <equinox@spreadspace.org>2015-03-31 22:39:17 (GMT)
commit53ea950cc919d0a57b94eaa443bccf9d7d6cdcbf (patch)
tree16f33f427537393cfe21744464a709e7ce975e81 /hardware/RedunDC
parent32d6511e037c3560c802b6910b3dc9cb46bf6467 (diff)
coarse plasing finished
Diffstat (limited to 'hardware/RedunDC')
-rw-r--r--hardware/RedunDC/RedunDC.cmp16
-rw-r--r--hardware/RedunDC/RedunDC.kicad_pcb1208
-rw-r--r--hardware/RedunDC/RedunDC.pro78
3 files changed, 1247 insertions, 55 deletions
diff --git a/hardware/RedunDC/RedunDC.cmp b/hardware/RedunDC/RedunDC.cmp
index 1351448..e7cbfb1 100644
--- a/hardware/RedunDC/RedunDC.cmp
+++ b/hardware/RedunDC/RedunDC.cmp
@@ -1,10 +1,10 @@
-Cmp-Mod V01 Created by CvPcb (22-Jun-2014 BZR 4027)-stable date = Die 31 Mär 2015 20:14:17 CEST
+Cmp-Mod V01 Created by CvPcb (22-Jun-2014 BZR 4027)-stable date = Mit 01 Apr 2015 00:17:14 CEST
BeginCmp
TimeStamp = /551AE068;
Reference = C1;
ValeurCmp = CP1;
-IdModule = ;
+IdModule = SM2917POL;
EndCmp
BeginCmp
@@ -18,7 +18,7 @@ BeginCmp
TimeStamp = /551ADF4F;
Reference = D1;
ValeurCmp = TVS;
-IdModule = ;
+IdModule = SOD123W;
EndCmp
BeginCmp
@@ -32,14 +32,14 @@ BeginCmp
TimeStamp = /551ADF5E;
Reference = D3;
ValeurCmp = DIODESCH;
-IdModule = ;
+IdModule = DO-214AC;
EndCmp
BeginCmp
TimeStamp = /551ADF6B;
Reference = D4;
ValeurCmp = DIODESCH;
-IdModule = ;
+IdModule = DO-214AC;
EndCmp
BeginCmp
@@ -53,21 +53,21 @@ BeginCmp
TimeStamp = /551ADF85;
Reference = D6;
ValeurCmp = TVS;
-IdModule = ;
+IdModule = SOD123W;
EndCmp
BeginCmp
TimeStamp = /551ADEE0;
Reference = F1;
ValeurCmp = Polyfuse;
-IdModule = ;
+IdModule = LF2016L;
EndCmp
BeginCmp
TimeStamp = /551ADED1;
Reference = F2;
ValeurCmp = Polyfuse;
-IdModule = ;
+IdModule = LF2016L;
EndCmp
BeginCmp
diff --git a/hardware/RedunDC/RedunDC.kicad_pcb b/hardware/RedunDC/RedunDC.kicad_pcb
index 6326f1f..66abf48 100644
--- a/hardware/RedunDC/RedunDC.kicad_pcb
+++ b/hardware/RedunDC/RedunDC.kicad_pcb
@@ -1,15 +1,15 @@
(kicad_pcb (version 3) (host pcbnew "(22-Jun-2014 BZR 4027)-stable")
(general
- (links 0)
- (no_connects 0)
- (area 0 0 0 0)
+ (links 28)
+ (no_connects 28)
+ (area 151.230112 124.15393 198.527888 157.8926)
(thickness 1.6)
- (drawings 0)
+ (drawings 4)
(tracks 0)
(zones 0)
- (modules 0)
- (nets 1)
+ (modules 23)
+ (nets 11)
)
(page A3)
@@ -37,7 +37,7 @@
)
(setup
- (last_trace_width 0.2032)
+ (last_trace_width 1.8009)
(user_trace_width 0.2032)
(user_trace_width 0.3988)
(user_trace_width 0.701)
@@ -68,8 +68,8 @@
(mod_edge_width 0.15)
(mod_text_size 1 1)
(mod_text_width 0.15)
- (pad_size 1.5 1.5)
- (pad_drill 0.6)
+ (pad_size 5 5)
+ (pad_drill 3)
(pad_to_mask_clearance 0)
(aux_axis_origin 0 0)
(visible_elements FFFFFFBF)
@@ -102,6 +102,16 @@
)
(net 0 "")
+ (net 1 GND)
+ (net 2 N-000001)
+ (net 3 N-0000010)
+ (net 4 N-000002)
+ (net 5 N-000003)
+ (net 6 N-000004)
+ (net 7 N-000006)
+ (net 8 N-000008)
+ (net 9 N-000009)
+ (net 10 VCC)
(net_class Default "Dies ist die voreingestellte Netzklasse."
(clearance 0.1524)
@@ -111,6 +121,1186 @@
(uvia_dia 0.508)
(uvia_drill 0.127)
(add_net "")
+ (add_net GND)
+ (add_net N-000001)
+ (add_net N-0000010)
+ (add_net N-000002)
+ (add_net N-000003)
+ (add_net N-000004)
+ (add_net N-000006)
+ (add_net N-000008)
+ (add_net N-000009)
+ (add_net VCC)
+ )
+
+ (module SOT23-5 (layer B.Cu) (tedit 4ECF78EF) (tstamp 551B1D04)
+ (at 174.2186 149.8346)
+ (path /551AE3F4)
+ (attr smd)
+ (fp_text reference U1 (at 2.19964 0.29972 270) (layer B.SilkS)
+ (effects (font (size 0.635 0.635) (thickness 0.127)) (justify mirror))
+ )
+ (fp_text value M74VHC1GT08 (at 0 0) (layer B.SilkS)
+ (effects (font (size 0.635 0.635) (thickness 0.127)) (justify mirror))
+ )
+ (fp_line (start 1.524 0.889) (end 1.524 -0.889) (layer B.SilkS) (width 0.127))
+ (fp_line (start 1.524 -0.889) (end -1.524 -0.889) (layer B.SilkS) (width 0.127))
+ (fp_line (start -1.524 -0.889) (end -1.524 0.889) (layer B.SilkS) (width 0.127))
+ (fp_line (start -1.524 0.889) (end 1.524 0.889) (layer B.SilkS) (width 0.127))
+ (pad 1 smd rect (at -0.9525 -1.27) (size 0.508 0.762)
+ (layers B.Cu B.Paste B.Mask)
+ (net 9 N-000009)
+ )
+ (pad 3 smd rect (at 0.9525 -1.27) (size 0.508 0.762)
+ (layers B.Cu B.Paste B.Mask)
+ (net 1 GND)
+ )
+ (pad 5 smd rect (at -0.9525 1.27) (size 0.508 0.762)
+ (layers B.Cu B.Paste B.Mask)
+ (net 10 VCC)
+ )
+ (pad 2 smd rect (at 0 -1.27) (size 0.508 0.762)
+ (layers B.Cu B.Paste B.Mask)
+ (net 8 N-000008)
+ )
+ (pad 4 smd rect (at 0.9525 1.27) (size 0.508 0.762)
+ (layers B.Cu B.Paste B.Mask)
+ (net 7 N-000006)
+ )
+ (model smd/SOT23_5.wrl
+ (at (xyz 0 0 0))
+ (scale (xyz 0.1 0.1 0.1))
+ (rotate (xyz 0 0 0))
+ )
+ )
+
+ (module SOD123W (layer B.Cu) (tedit 551B1C00) (tstamp 551B1D10)
+ (at 167.9956 137.8204 270)
+ (path /551ADF4F)
+ (fp_text reference D1 (at 0 1.25 270) (layer B.SilkS)
+ (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+ )
+ (fp_text value TVS (at 0 -1.4 270) (layer B.SilkS)
+ (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+ )
+ (fp_line (start 0.8 1.05) (end 0.8 -1.05) (layer B.SilkS) (width 0.15))
+ (fp_line (start 0.95 1.05) (end 0.95 -1.05) (layer B.SilkS) (width 0.15))
+ (fp_line (start -1.45 1.05) (end 1.45 1.05) (layer B.SilkS) (width 0.15))
+ (fp_line (start 1.45 1.05) (end 1.45 -1.05) (layer B.SilkS) (width 0.15))
+ (fp_line (start 1.45 -1.05) (end -1.45 -1.05) (layer B.SilkS) (width 0.15))
+ (fp_line (start -1.45 -1.05) (end -1.45 1.05) (layer B.SilkS) (width 0.15))
+ (pad 1 smd rect (at -1.4 0 270) (size 1.2 1.2)
+ (layers B.Cu B.Paste B.Mask)
+ (net 1 GND)
+ )
+ (pad 2 smd rect (at 1.4 0 270) (size 1.2 1.2)
+ (layers B.Cu B.Paste B.Mask)
+ (net 2 N-000001)
+ )
+ )
+
+ (module SOD123W (layer B.Cu) (tedit 551B1C00) (tstamp 551B1D1C)
+ (at 180.1622 137.6172 270)
+ (path /551ADF85)
+ (fp_text reference D6 (at 0 1.25 270) (layer B.SilkS)
+ (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+ )
+ (fp_text value TVS (at 0 -1.4 270) (layer B.SilkS)
+ (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+ )
+ (fp_line (start 0.8 1.05) (end 0.8 -1.05) (layer B.SilkS) (width 0.15))
+ (fp_line (start 0.95 1.05) (end 0.95 -1.05) (layer B.SilkS) (width 0.15))
+ (fp_line (start -1.45 1.05) (end 1.45 1.05) (layer B.SilkS) (width 0.15))
+ (fp_line (start 1.45 1.05) (end 1.45 -1.05) (layer B.SilkS) (width 0.15))
+ (fp_line (start 1.45 -1.05) (end -1.45 -1.05) (layer B.SilkS) (width 0.15))
+ (fp_line (start -1.45 -1.05) (end -1.45 1.05) (layer B.SilkS) (width 0.15))
+ (pad 1 smd rect (at -1.4 0 270) (size 1.2 1.2)
+ (layers B.Cu B.Paste B.Mask)
+ (net 1 GND)
+ )
+ (pad 2 smd rect (at 1.4 0 270) (size 1.2 1.2)
+ (layers B.Cu B.Paste B.Mask)
+ (net 3 N-0000010)
+ )
+ )
+
+ (module SM2917POL (layer B.Cu) (tedit 551B1470) (tstamp 551B1D27)
+ (at 174.0916 136.144)
+ (path /551AE068)
+ (fp_text reference C1 (at 0 -1) (layer B.SilkS)
+ (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+ )
+ (fp_text value CP1 (at 0 0.7) (layer B.SilkS)
+ (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
+ )
+ (fp_line (start -1.95 2.15) (end -1.95 -2.15) (layer B.SilkS) (width 0.15))
+ (fp_line (start -3.65 2.15) (end 3.65 2.15) (layer B.SilkS) (width 0.15))
+ (fp_line (start 3.65 2.15) (end 3.65 -2.15) (layer B.SilkS) (width 0.15))
+ (fp_line (start 3.65 -2.15) (end -3.65 -2.15) (layer B.SilkS) (width 0.15))
+ (fp_line (start -3.65 -2.15) (end -3.65 2.15) (layer B.SilkS) (width 0.15))
+ (pad 1 smd rect (at -3.25 0) (size 2.1 3)
+ (layers B.Cu B.Paste B.Mask)
+ (net 5 N-000003)
+ )
+ (pad 2 smd rect (at 3.25 0) (size 2.1 3)
+ (layers B.Cu B.Paste B.Mask)
+ (net 1 GND)
+ )
+ )
+
+ (module SM0805 (layer B.Cu) (tedit 5091495C) (tstamp 551B1D34)
+ (at 170.7642 149.8092 90)
+ (path /551AE174)
+ (attr smd)
+ (fp_text reference C2 (at 0 0.3175 90) (layer B.SilkS)
+ (effects (font (size 0.50038 0.50038) (thickness 0.10922)) (justify mirror))
+ )
+ (fp_text value 100nF (at 0 -0.381 90) (layer B.SilkS)
+ (effects (font (size 0.50038 0.50038) (thickness 0.10922)) (justify mirror))
+ )
+ (fp_circle (center -1.651 -0.762) (end -1.651 -0.635) (layer B.SilkS) (width 0.09906))
+ (fp_line (start -0.508 -0.762) (end -1.524 -0.762) (layer B.SilkS) (width 0.09906))
+ (fp_line (start -1.524 -0.762) (end -1.524 0.762) (layer B.SilkS) (width 0.09906))
+ (fp_line (start -1.524 0.762) (end -0.508 0.762) (layer B.SilkS) (width 0.09906))
+ (fp_line (start 0.508 0.762) (end 1.524 0.762) (layer B.SilkS) (width 0.09906))
+ (fp_line (start 1.524 0.762) (end 1.524 -0.762) (layer B.SilkS) (width 0.09906))
+ (fp_line (start 1.524 -0.762) (end 0.508 -0.762) (layer B.SilkS) (width 0.09906))
+ (pad 1 smd rect (at -0.9525 0 90) (size 0.889 1.397)
+ (layers B.Cu B.Paste B.Mask)
+ (net 10 VCC)
+ )
+ (pad 2 smd rect (at 0.9525 0 90) (size 0.889 1.397)
+ (layers B.Cu B.Paste B.Mask)
+ (net 1 GND)
+ )
+ (model smd/chip_cms.wrl
+ (at (xyz 0 0 0))
+ (scale (xyz 0.1 0.1 0.1))
+ (rotate (xyz 0 0 0))
+ )
+ )
+
+ (module SM0805 (layer B.Cu) (tedit 5091495C) (tstamp 551B1D41)
+ (at 182.6006 137.6426 90)
+ (path /551ADFF8)
+ (attr smd)
+ (fp_text reference R2 (at 0 0.3175 90) (layer B.SilkS)
+ (effects (font (size 0.50038 0.50038) (thickness 0.10922)) (justify mirror))
+ )
+ (fp_text value R (at 0 -0.381 90) (layer B.SilkS)
+ (effects (font (size 0.50038 0.50038) (thickness 0.10922)) (justify mirror))
+ )
+ (fp_circle (center -1.651 -0.762) (end -1.651 -0.635) (layer B.SilkS) (width 0.09906))
+ (fp_line (start -0.508 -0.762) (end -1.524 -0.762) (layer B.SilkS) (width 0.09906))
+ (fp_line (start -1.524 -0.762) (end -1.524 0.762) (layer B.SilkS) (width 0.09906))
+ (fp_line (start -1.524 0.762) (end -0.508 0.762) (layer B.SilkS) (width 0.09906))
+ (fp_line (start 0.508 0.762) (end 1.524 0.762) (layer B.SilkS) (width 0.09906))
+ (fp_line (start 1.524 0.762) (end 1.524 -0.762) (layer B.SilkS) (width 0.09906))
+ (fp_line (start 1.524 -0.762) (end 0.508 -0.762) (layer B.SilkS) (width 0.09906))
+ (pad 1 smd rect (at -0.9525 0 90) (size 0.889 1.397)
+ (layers B.Cu B.Paste B.Mask)
+ (net 3 N-0000010)
+ )
+ (pad 2 smd rect (at 0.9525 0 90) (size 0.889 1.397)
+ (layers B.Cu B.Paste B.Mask)
+ (net 8 N-000008)
+ )
+ (model smd/chip_cms.wrl
+ (at (xyz 0 0 0))
+ (scale (xyz 0.1 0.1 0.1))
+ (rotate (xyz 0 0 0))
+ )
+ )
+
+ (module SM0805 (layer B.Cu) (tedit 5091495C) (tstamp 551B1D4E)
+ (at 165.4302 137.8204 90)
+ (path /551AE015)
+ (attr smd)
+ (fp_text reference R1 (at 0 0.3175 90) (layer B.SilkS)
+ (effects (font (size 0.50038 0.50038) (thickness 0.10922)) (justify mirror))
+ )
+ (fp_text value R (at 0 -0.381 90) (layer B.SilkS)
+ (effects (font (size 0.50038 0.50038) (thickness 0.10922)) (justify mirror))
+ )
+ (fp_circle (center -1.651 -0.762) (end -1.651 -0.635) (layer B.SilkS) (width 0.09906))
+ (fp_line (start -0.508 -0.762) (end -1.524 -0.762) (layer B.SilkS) (width 0.09906))
+ (fp_line (start -1.524 -0.762) (end -1.524 0.762) (layer B.SilkS) (width 0.09906))
+ (fp_line (start -1.524 0.762) (end -0.508 0.762) (layer B.SilkS) (width 0.09906))
+ (fp_line (start 0.508 0.762) (end 1.524 0.762) (layer B.SilkS) (width 0.09906))
+ (fp_line (start 1.524 0.762) (end 1.524 -0.762) (layer B.SilkS) (width 0.09906))
+ (fp_line (start 1.524 -0.762) (end 0.508 -0.762) (layer B.SilkS) (width 0.09906))
+ (pad 1 smd rect (at -0.9525 0 90) (size 0.889 1.397)
+ (layers B.Cu B.Paste B.Mask)
+ (net 2 N-000001)
+ )
+ (pad 2 smd rect (at 0.9525 0 90) (size 0.889 1.397)
+ (layers B.Cu B.Paste B.Mask)
+ (net 9 N-000009)
+ )
+ (model smd/chip_cms.wrl
+ (at (xyz 0 0 0))
+ (scale (xyz 0.1 0.1 0.1))
+ (rotate (xyz 0 0 0))
+ )
+ )
+
+ (module SIL-3 (layer F.Cu) (tedit 200000) (tstamp 551B1D5A)
+ (at 175.3616 154.1018)
+ (descr "Connecteur 3 pins")
+ (tags "CONN DEV")
+ (path /551AE11C)
+ (fp_text reference K1 (at 0 -2.54) (layer F.SilkS)
+ (effects (font (size 1.7907 1.07696) (thickness 0.3048)))
+ )
+ (fp_text value STATUS (at 0 -2.54) (layer F.SilkS) hide
+ (effects (font (size 1.524 1.016) (thickness 0.3048)))
+ )
+ (fp_line (start -3.81 1.27) (end -3.81 -1.27) (layer F.SilkS) (width 0.3048))
+ (fp_line (start -3.81 -1.27) (end 3.81 -1.27) (layer F.SilkS) (width 0.3048))
+ (fp_line (start 3.81 -1.27) (end 3.81 1.27) (layer F.SilkS) (width 0.3048))
+ (fp_line (start 3.81 1.27) (end -3.81 1.27) (layer F.SilkS) (width 0.3048))
+ (fp_line (start -1.27 -1.27) (end -1.27 1.27) (layer F.SilkS) (width 0.3048))
+ (pad 1 thru_hole rect (at -2.54 0) (size 1.397 1.397) (drill 0.8128)
+ (layers *.Cu *.Mask F.SilkS)
+ (net 10 VCC)
+ )
+ (pad 2 thru_hole circle (at 0 0) (size 1.397 1.397) (drill 0.8128)
+ (layers *.Cu *.Mask F.SilkS)
+ (net 7 N-000006)
+ )
+ (pad 3 thru_hole circle (at 2.54 0) (size 1.397 1.397) (drill 0.8128)
+ (layers *.Cu *.Mask F.SilkS)
+ (net 1 GND)
+ )
+ )
+
+ (module SIL-2 (layer F.Cu) (tedit 200000) (tstamp 551B1D64)
+ (at 160.5534 142.9258 90)
+ (descr "Connecteurs 2 pins")
+ (tags "CONN DEV")
+ (path /551AE10D)
+ (fp_text reference P1 (at 0 -2.54 90) (layer F.SilkS)
+ (effects (font (size 1.72974 1.08712) (thickness 0.3048)))
+ )
+ (fp_text value Vin1 (at 0 -2.54 90) (layer F.SilkS) hide
+ (effects (font (size 1.524 1.016) (thickness 0.3048)))
+ )
+ (fp_line (start -2.54 1.27) (end -2.54 -1.27) (layer F.SilkS) (width 0.3048))
+ (fp_line (start -2.54 -1.27) (end 2.54 -1.27) (layer F.SilkS) (width 0.3048))
+ (fp_line (start 2.54 -1.27) (end 2.54 1.27) (layer F.SilkS) (width 0.3048))
+ (fp_line (start 2.54 1.27) (end -2.54 1.27) (layer F.SilkS) (width 0.3048))
+ (pad 1 thru_hole rect (at -1.27 0 90) (size 1.397 1.397) (drill 0.8128)
+ (layers *.Cu *.Mask F.SilkS)
+ (net 6 N-000004)
+ )
+ (pad 2 thru_hole circle (at 1.27 0 90) (size 1.397 1.397) (drill 0.8128)
+ (layers *.Cu *.Mask F.SilkS)
+ (net 1 GND)
+ )
+ )
+
+ (module SIL-2 (layer F.Cu) (tedit 200000) (tstamp 551B1D6E)
+ (at 187.198 142.7988 90)
+ (descr "Connecteurs 2 pins")
+ (tags "CONN DEV")
+ (path /551AE0FE)
+ (fp_text reference P3 (at 0 -2.54 90) (layer F.SilkS)
+ (effects (font (size 1.72974 1.08712) (thickness 0.3048)))
+ )
+ (fp_text value Vin2 (at 0 -2.54 90) (layer F.SilkS) hide
+ (effects (font (size 1.524 1.016) (thickness 0.3048)))
+ )
+ (fp_line (start -2.54 1.27) (end -2.54 -1.27) (layer F.SilkS) (width 0.3048))
+ (fp_line (start -2.54 -1.27) (end 2.54 -1.27) (layer F.SilkS) (width 0.3048))
+ (fp_line (start 2.54 -1.27) (end 2.54 1.27) (layer F.SilkS) (width 0.3048))
+ (fp_line (start 2.54 1.27) (end -2.54 1.27) (layer F.SilkS) (width 0.3048))
+ (pad 1 thru_hole rect (at -1.27 0 90) (size 1.397 1.397) (drill 0.8128)
+ (layers *.Cu *.Mask F.SilkS)
+ (net 4 N-000002)
+ )
+ (pad 2 thru_hole circle (at 1.27 0 90) (size 1.397 1.397) (drill 0.8128)
+ (layers *.Cu *.Mask F.SilkS)
+ (net 1 GND)
+ )
+ )
+
+ (module SIL-2 (layer F.Cu) (tedit 200000) (tstamp 551B1D78)
+ (at 175.4632 127.8636)
+ (descr "Connecteurs 2 pins")
+ (tags "CONN DEV")
+ (path /551AE0C7)
+ (fp_text reference P2 (at 0 -2.54) (layer F.SilkS)
+ (effects (font (size 1.72974 1.08712) (thickness 0.3048)))
+ )
+ (fp_text value Vout (at 0 -2.54) (layer F.SilkS) hide
+ (effects (font (size 1.524 1.016) (thickness 0.3048)))
+ )
+ (fp_line (start -2.54 1.27) (end -2.54 -1.27) (layer F.SilkS) (width 0.3048))
+ (fp_line (start -2.54 -1.27) (end 2.54 -1.27) (layer F.SilkS) (width 0.3048))
+ (fp_line (start 2.54 -1.27) (end 2.54 1.27) (layer F.SilkS) (width 0.3048))
+ (fp_line (start 2.54 1.27) (end -2.54 1.27) (layer F.SilkS) (width 0.3048))
+ (pad 1 thru_hole rect (at -1.27 0) (size 1.397 1.397) (drill 0.8128)
+ (layers *.Cu *.Mask F.SilkS)
+ (net 5 N-000003)
+ )
+ (pad 2 thru_hole circle (at 1.27 0) (size 1.397 1.397) (drill 0.8128)
+ (layers *.Cu *.Mask F.SilkS)
+ (net 1 GND)
+ )
+ )
+
+ (module LF2016L (layer B.Cu) (tedit 551B1747) (tstamp 551B1D82)
+ (at 166.878 143.8402)
+ (path /551ADEE0)
+ (fp_text reference F1 (at 0 0.95) (layer B.SilkS)
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diff --git a/hardware/RedunDC/RedunDC.pro b/hardware/RedunDC/RedunDC.pro
index c2d28c4..891dd58 100644
--- a/hardware/RedunDC/RedunDC.pro
+++ b/hardware/RedunDC/RedunDC.pro
@@ -1,47 +1,11 @@
-update=Die 31 Mär 2015 20:04:06 CEST
+update=Mit 01 Apr 2015 00:32:46 CEST
version=1
-last_client=eeschema
+last_client=pcbnew
[cvpcb]
version=1
NetIExt=net
[cvpcb/libraries]
EquName1=devcms
-[pcbnew]
-version=1
-LastNetListRead=
-UseCmpFile=1
-PadDrill=0.600000000000
-PadDrillOvalY=0.600000000000
-PadSizeH=1.500000000000
-PadSizeV=1.500000000000
-PcbTextSizeV=1.500000000000
-PcbTextSizeH=1.500000000000
-PcbTextThickness=0.300000000000
-ModuleTextSizeV=1.000000000000
-ModuleTextSizeH=1.000000000000
-ModuleTextSizeThickness=0.150000000000
-SolderMaskClearance=0.000000000000
-SolderMaskMinWidth=0.000000000000
-DrawSegmentWidth=0.200000000000
-BoardOutlineThickness=0.100000000000
-ModuleOutlineThickness=0.150000000000
-[pcbnew/libraries]
-LibDir=/home/equinox/spreadspace/kicad/libs
-LibName1=sockets
-LibName2=connect
-LibName3=discret
-LibName4=pin_array
-LibName5=divers
-LibName6=smd_capacitors
-LibName7=smd_resistors
-LibName8=smd_transistors
-LibName9=libcms
-LibName10=display
-LibName11=led
-LibName12=dip_sockets
-LibName13=pga_sockets
-LibName14=valves
-LibName15=spreadspace
[general]
version=1
[eeschema]
@@ -84,3 +48,41 @@ LibName28=atmel
LibName29=contrib
LibName30=valves
LibName31=RedunDC
+[pcbnew]
+version=1
+LastNetListRead=RedunDC.net
+UseCmpFile=1
+PadDrill=3.000000000000
+PadDrillOvalY=3.000000000000
+PadSizeH=5.000000000000
+PadSizeV=5.000000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[pcbnew/libraries]
+LibDir=../lib
+LibName1=sockets
+LibName2=connect
+LibName3=discret
+LibName4=pin_array
+LibName5=divers
+LibName6=smd_capacitors
+LibName7=smd_resistors
+LibName8=smd_transistors
+LibName9=libcms
+LibName10=display
+LibName11=led
+LibName12=dip_sockets
+LibName13=pga_sockets
+LibName14=valves
+LibName15=RedunDC
+LibName16=rhlogo
+LibName17=oshw-logo
generated by cgit v0.10.2 at 2024-06-29 10:44:29 (GMT)