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authorChristian Pointner <equinox@spreadspace.org>2015-03-31 17:51:38 (GMT)
committerChristian Pointner <equinox@spreadspace.org>2015-03-31 17:51:38 (GMT)
commit03748640f6a664fab86391940504eb77526f678e (patch)
tree7d86a14aecf794225f8f7848f7de78118f147e16 /hardware/RedunDC/RedunDC.kicad_pcb
parent243ce9017f48811dd649ed984d24c0bc0ce601fe (diff)
added empty kicad project
Diffstat (limited to 'hardware/RedunDC/RedunDC.kicad_pcb')
-rw-r--r--hardware/RedunDC/RedunDC.kicad_pcb116
1 files changed, 116 insertions, 0 deletions
diff --git a/hardware/RedunDC/RedunDC.kicad_pcb b/hardware/RedunDC/RedunDC.kicad_pcb
new file mode 100644
index 0000000..6326f1f
--- /dev/null
+++ b/hardware/RedunDC/RedunDC.kicad_pcb
@@ -0,0 +1,116 @@
+(kicad_pcb (version 3) (host pcbnew "(22-Jun-2014 BZR 4027)-stable")
+
+ (general
+ (links 0)
+ (no_connects 0)
+ (area 0 0 0 0)
+ (thickness 1.6)
+ (drawings 0)
+ (tracks 0)
+ (zones 0)
+ (modules 0)
+ (nets 1)
+ )
+
+ (page A3)
+ (title_block
+ (rev 1)
+ (company "Radio Helsinki: RedunDC")
+ )
+
+ (layers
+ (15 F.Cu signal)
+ (0 B.Cu signal)
+ (16 B.Adhes user)
+ (17 F.Adhes user)
+ (18 B.Paste user)
+ (19 F.Paste user)
+ (20 B.SilkS user)
+ (21 F.SilkS user)
+ (22 B.Mask user)
+ (23 F.Mask user)
+ (24 Dwgs.User user)
+ (25 Cmts.User user)
+ (26 Eco1.User user)
+ (27 Eco2.User user)
+ (28 Edge.Cuts user)
+ )
+
+ (setup
+ (last_trace_width 0.2032)
+ (user_trace_width 0.2032)
+ (user_trace_width 0.3988)
+ (user_trace_width 0.701)
+ (user_trace_width 1.0008)
+ (user_trace_width 1.8009)
+ (trace_clearance 0.1524)
+ (zone_clearance 0.508)
+ (zone_45_only no)
+ (trace_min 0.1524)
+ (segment_width 0.2)
+ (edge_width 0.1)
+ (via_size 0.6502)
+ (via_drill 0.3023)
+ (via_min_size 0.5004)
+ (via_min_drill 0.3023)
+ (user_via 0.6502 0.3023)
+ (user_via 0.7493 0.3988)
+ (user_via 0.95 0.3988)
+ (user_via 1.1989 0.4496)
+ (user_via 1.999 0.5004)
+ (uvia_size 0.508)
+ (uvia_drill 0.127)
+ (uvias_allowed no)
+ (uvia_min_size 0.508)
+ (uvia_min_drill 0.127)
+ (pcb_text_width 0.3)
+ (pcb_text_size 1.5 1.5)
+ (mod_edge_width 0.15)
+ (mod_text_size 1 1)
+ (mod_text_width 0.15)
+ (pad_size 1.5 1.5)
+ (pad_drill 0.6)
+ (pad_to_mask_clearance 0)
+ (aux_axis_origin 0 0)
+ (visible_elements FFFFFFBF)
+ (pcbplotparams
+ (layerselection 3178497)
+ (usegerberextensions true)
+ (excludeedgelayer true)
+ (linewidth 0.150000)
+ (plotframeref false)
+ (viasonmask false)
+ (mode 1)
+ (useauxorigin false)
+ (hpglpennumber 1)
+ (hpglpenspeed 20)
+ (hpglpendiameter 15)
+ (hpglpenoverlay 2)
+ (psnegative false)
+ (psa4output false)
+ (plotreference true)
+ (plotvalue true)
+ (plotothertext true)
+ (plotinvisibletext false)
+ (padsonsilk false)
+ (subtractmaskfromsilk false)
+ (outputformat 1)
+ (mirror false)
+ (drillshape 1)
+ (scaleselection 1)
+ (outputdirectory ""))
+ )
+
+ (net 0 "")
+
+ (net_class Default "Dies ist die voreingestellte Netzklasse."
+ (clearance 0.1524)
+ (trace_width 0.2032)
+ (via_dia 0.6502)
+ (via_drill 0.3023)
+ (uvia_dia 0.508)
+ (uvia_drill 0.127)
+ (add_net "")
+ )
+
+)