// SPDX-License-Identifier: GPL-2.0-or-later /* * Support for Digigram AlpX PCI-e boards * * Copyright (c) 2024 Digigram Digital (info@digigram.com) */ #ifndef _ALPX_VARIANTS_STEREO_H_ #define _ALPX_VARIANTS_STEREO_H_ #include "alpx.h" #include "alpx_reg.h" #include #include "alpx_variants_common.h" /* Specifications of stereo cards */ /* Alp222 clock controls */ static const char *alp222_control_choice_clk_src_entries[ALP222_CLK_MANAGER_CLK_SRC_QTY] = { "Internal","SIC","Word Clk", "AES Syn", "AES Aud", }; /* Same order than the constants values */ static u32 alp222_control_choice_clk_src_entries_values[ALP222_CLK_MANAGER_CLK_SRC_QTY] = { ALP222_CLK_MANAGER_CLK_SRC_INTERNAL, ALP222_CLK_MANAGER_CLK_SRC_SIC, ALP222_CLK_MANAGER_CLK_SRC_WCLK, ALP222_CLK_MANAGER_CLK_SRC_AES_SYNC, ALP222_CLK_MANAGER_CLK_SRC_AES_AUDIO, }; /** 222 **/ static struct snd_pcm_hardware alp222_hardware_specs = { .info = SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_RESUME, .formats = SNDRV_PCM_FMTBIT_S32_LE, .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_192000, .rate_min = 8000, .rate_max = 192000, .channels_min = 4, .channels_max = 4, .buffer_bytes_max = 64 * SZ_1K * 4, /* period_bytes_max * periods_max */ .period_bytes_min = 48, /* min latency 1ms */ .period_bytes_max = 64 * SZ_1K, /* 20ms at 192kHz * nchans * 4B, rounded at 2^n */ .periods_min = 1, .periods_max = 4, }; /* Alp 222e LINE */ static const DECLARE_TLV_DB_MINMAX_MUTE(alp222_line_analog_gains_scale, ALP222_ANALOG_EQ_GAIN_MIN_cdB, ALP222_ANALOG_EQ_GAIN_MAX_cdB); /* Note : use ALPX_GAIN_REG(0) to jump to the actual parameters's registers */ static struct alpx_control_descriptor alp222_control_descriptors[] = { /* INPUT Amplification */ { .type = ALPX_CONTROL_TYPE_AMPLIFIER, .base = ALP222_ANALOG_CAPTURE_AMPLI_BASE, .prefix = "Ana Capture", .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_TLV_READ, .data.ampli = { .gains_scale = alpxxx_line_digital_gains_scale, .reg_gain_min = ALP_AMPLIFIER_GAIN_MIN_REG, .reg_gain_max = ALP_AMPLIFIER_GAIN_MAX_REG, .lines_count = ALP222_ANALOG_QTY, }, }, { .type = ALPX_CONTROL_TYPE_AMPLIFIER, .base = ALP222_AES3_CAPTURE_AMPLI_BASE, .prefix = "AES Capture", .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_TLV_READ, .data.ampli = { .gains_scale = alpxxx_line_digital_gains_scale, .reg_gain_min = ALP_AMPLIFIER_GAIN_MIN_REG, .reg_gain_max = ALP_AMPLIFIER_GAIN_MAX_REG, .lines_count = ALP222_AES3_QTY, }, }, { .type = ALPX_CONTROL_TYPE_AMPLIFIER, .base = ALP222_DAW_PLAYBACK_AMPLI_BASE, .prefix = "DAW Playback", .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_TLV_READ, .data.ampli = { .gains_scale = alpxxx_line_digital_gains_scale, .reg_gain_min = ALP_AMPLIFIER_GAIN_MIN_REG, .reg_gain_max = ALP_AMPLIFIER_GAIN_MAX_REG, .lines_count = ALP222_DAW_QTY, }, }, /* OUTPUT Amplification*/ { .type = ALPX_CONTROL_TYPE_AMPLIFIER, .base = ALP222_ANALOG_PLAYBACK_AMPLI_BASE, .prefix = "Ana Playback", .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_TLV_READ, .data.ampli = { .gains_scale = alpxxx_line_digital_gains_scale, .reg_gain_min = ALP_AMPLIFIER_GAIN_MIN_REG, .reg_gain_max = ALP_AMPLIFIER_GAIN_MAX_REG, .lines_count = ALP222_ANALOG_QTY, }, }, { .type = ALPX_CONTROL_TYPE_AMPLIFIER, .base = ALP222_AES3_PLAYBACK_AMPLI_BASE, .prefix = "AES Playback", .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_TLV_READ, .data.ampli = { .gains_scale = alpxxx_line_digital_gains_scale, .reg_gain_min = ALP_AMPLIFIER_GAIN_MIN_REG, .reg_gain_max = ALP_AMPLIFIER_GAIN_MAX_REG, .lines_count = ALP222_AES3_QTY, }, }, { .type = ALPX_CONTROL_TYPE_AMPLIFIER, .base = ALP222_DAW_CAPTURE_AMPLI_BASE , .prefix = "DAW Capture", .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_TLV_READ, .data.ampli = { .gains_scale = alpxxx_line_digital_gains_scale, .reg_gain_min = ALP_AMPLIFIER_GAIN_MIN_REG, .reg_gain_max = ALP_AMPLIFIER_GAIN_MAX_REG, .lines_count = ALP222_DAW_QTY, }, }, /* Analog Eq */ { .type = ALPX_CONTROL_TYPE_ANALOG_EQ, .base = ALP222_CODEC_CTRL_BASE, .prefix = "Codec Analog Capture", .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_TLV_READ, .data.codec = { .offset = ALP222_CODEC_PGA_REGS, .gains_scale = alp222_line_analog_gains_scale, .reg_gain_min = ALP222_ANALOG_EQ_GAIN_MIN_REG, .reg_gain_max = ALP222_ANALOG_EQ_GAIN_MAX_REG, .lines_count = ALP222_ANALOG_QTY, }, }, /* Mixer */ { .type = ALPX_CONTROL_TYPE_MIXER, .base = ALP222_MIXER_BASE, .prefix = "Mxr", .access = SNDRV_CTL_ELEM_ACCESS_READWRITE| SNDRV_CTL_ELEM_ACCESS_TLV_READ, .data.mixer = { .lines_count = ALP222_MIXER_SIZE, .gains_scale = alpxxx_line_digital_gains_scale, .reg_gain_min = ALP_AMPLIFIER_GAIN_MIN_REG, .reg_gain_max = ALP_AMPLIFIER_GAIN_MAX_REG, }, }, /* Clock sources Read Only */ { .type = ALPX_CONTROL_TYPE_CHOICE, .base = ALP222_CLK_MANAGER_BASE, .prefix = "Clk Src", .access = SNDRV_CTL_ELEM_ACCESS_READ, .data.choice = { .offset = ALP222_CLK_MANAGER_CONFIG_REG, .mask = ALP222_CLK_MANAGER_CLK_SRC_MASK, .pos = ALP222_CLK_MANAGER_CLK_SRC_POS, .entries = alp222_control_choice_clk_src_entries, .entries_values = alp222_control_choice_clk_src_entries_values, .entries_count = ARRAY_SIZE(alp222_control_choice_clk_src_entries), }, }, /* Current Clock BASE Value Read Only */ { .type = ALPX_CONTROL_TYPE_CHOICE, .base = ALP222_CLK_MANAGER_BASE, .prefix = "Clk Eff", .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, .data.choice = { .offset = ALP222_CLK_MANAGER_CONFIG_REG, .mask = ALP222_CLK_MANAGER_CONFIG_CLK_CURRENT_VALUE_MASK, .pos = ALP222_CLK_MANAGER_CONFIG_CLK_CURRENT_VALUE_POS, .entries = alpxxx_control_choice_current_clk_values_entries, .entries_values = alpxxx_control_choice_current_clk_values_entries_values, .entries_count = ARRAY_SIZE(alpxxx_control_choice_current_clk_values_entries), }, }, /* Current Clock factor values Read Only : RESERVED to keep id order*/ { .type = ALPX_CONTROL_RESERVED, .base = ALP222_CLK_MANAGER_BASE, .prefix = "RESERVED", .access = SNDRV_CTL_ELEM_ACCESS_READ, }, /* AES SRC */ { .type = ALPX_CONTROL_TYPE_FLAG, .base = ALP222_CODEC_CTRL_BASE, .prefix = "AES SRC Disable", .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, .data.flag = { .offset = ALP222_CODEC_CTRL_ASRC_REG, .mask = ALP222_CODEC_CTRL_ASRC_MASK, .pos = ALP222_CODEC_CTRL_ASRC_POS, }, }, /* Clock UP on fail over enabled flag */ { .type = ALPX_CONTROL_TYPE_FLAG, .base = ALP_PROC_BASE, .prefix = "CkSc Up", .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, .data.flag = { .offset = ALP_PROC_FWCONFIG_REG, .mask = ALP_PROC_FWCONFIG_CLKSRC_UP_MASK, .pos = ALP_PROC_FWCONFIG_CLKSRC_UP_POS, }, }, /* Clock DOWN on fail over enabled flag */ { .type = ALPX_CONTROL_TYPE_FLAG, .base = ALP_PROC_BASE, .prefix = "CkSc Down", .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, .data.flag = { .offset = ALP_PROC_FWCONFIG_REG, .mask = ALP_PROC_FWCONFIG_CLKSRC_DOWN_MASK, .pos = ALP_PROC_FWCONFIG_CLKSRC_DOWN_POS, }, }, /* Clock Failover priority 0 TOP*/ { .type = ALPX_CONTROL_TYPE_CHOICE, .base = ALP_PROC_BASE, .prefix = "Clk P0", .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, .data.choice = { .offset = ALP_PROC_CLK_SOURCE_PRIO_REG, .mask = ALP_PROC_CLK_SOURCE_PRIO0_MASK, .pos = ALP_PROC_CLK_SOURCE_PRIO0_POS, .entries = alp222_control_choice_clk_src_entries, .entries_values = alp222_control_choice_clk_src_entries_values, .entries_count = ARRAY_SIZE(alp222_control_choice_clk_src_entries), }, }, /* Clock Failover priority 1 */ { .type = ALPX_CONTROL_TYPE_CHOICE, .base = ALP_PROC_BASE, .prefix = "Clk P1", .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, .data.choice = { .offset = ALP_PROC_CLK_SOURCE_PRIO_REG, .mask = ALP_PROC_CLK_SOURCE_PRIO1_MASK, .pos = ALP_PROC_CLK_SOURCE_PRIO1_POS, .entries = alp222_control_choice_clk_src_entries, .entries_values = alp222_control_choice_clk_src_entries_values, .entries_count = ARRAY_SIZE(alp222_control_choice_clk_src_entries), }, }, /* Clock Failover priority 2*/ { .type = ALPX_CONTROL_TYPE_CHOICE, .base = ALP_PROC_BASE, .prefix = "Clk P2", .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, .data.choice = { .offset = ALP_PROC_CLK_SOURCE_PRIO_REG, .mask = ALP_PROC_CLK_SOURCE_PRIO2_MASK, .pos = ALP_PROC_CLK_SOURCE_PRIO2_POS, .entries = alp222_control_choice_clk_src_entries, .entries_values = alp222_control_choice_clk_src_entries_values, .entries_count = ARRAY_SIZE(alp222_control_choice_clk_src_entries), }, }, /* Clock Failover priority 3 Bottom*/ { .type = ALPX_CONTROL_TYPE_CHOICE, .base = ALP_PROC_BASE, .prefix = "Clk P3", .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, .data.choice = { .offset = ALP_PROC_CLK_SOURCE_PRIO_REG, .mask = ALP_PROC_CLK_SOURCE_PRIO3_MASK, .pos = ALP_PROC_CLK_SOURCE_PRIO3_POS, .entries = alp222_control_choice_clk_src_entries, .entries_values = alp222_control_choice_clk_src_entries_values, .entries_count = ARRAY_SIZE(alp222_control_choice_clk_src_entries), }, }, }; static struct alpx_variant alp222_variant __attribute__((unused)) = { .shortname = "Alp222e", .longname = "Alp 222e", .model = ALPX_VARIANT_MODEL_ALP222, .mixername = "Alp222e_Mix", .features = ALPX_VARIANT_FEATURE_GPIOS, .control_descriptors = alp222_control_descriptors, .control_descriptors_count = ARRAY_SIZE(alp222_control_descriptors), .capture_hw = &alp222_hardware_specs, .playback_hw = &alp222_hardware_specs, .flash_golden_production_base = ALPxxx_FLASH_GOLDEN_PRODUCTION_BASE, .gpios = { .base = ALP222_GPIO_BASE, .inputs_reg_offset = ALP222_GPIO_INPUT_REG, .inputs_qty = ALP222_GPIO_INPUT_QTY, .outputs_reg_offset = ALP222_GPIO_OUTPUT_REG, .outputs_qty = ALP222_GPIO_OUTPUT_QTY, }, .flash_partitions.partitions = alpx_mtd_partitions, .flash_partitions.qty = ARRAY_SIZE(alpx_mtd_partitions), .flash_partitions.qty_for_fw_update = 1, }; /* Alp 222e-MIC Variant definition */ static const DECLARE_TLV_DB_MINMAX_MUTE(alp222_mic_control_scale, ALP222_MIC_GAIN_MIN_cdB, ALP222_MIC_GAIN_MAX_cdB); /* Alp222 MIC controls : superset of Alp222 controls. Don't know how to embed an array into antother as first items ? */ /* So I've copied the items !! */ static struct alpx_control_descriptor alp222_mic_control_descriptors[] = { /* INPUT Amplification */ { .type = ALPX_CONTROL_TYPE_AMPLIFIER, .base = ALP222_ANALOG_CAPTURE_AMPLI_BASE, .prefix = "Ana Capture", .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_TLV_READ, .data.ampli = { .gains_scale = alpxxx_line_digital_gains_scale, .reg_gain_min = ALP_AMPLIFIER_GAIN_MIN_REG, .reg_gain_max = ALP_AMPLIFIER_GAIN_MAX_REG, .lines_count = ALP222_ANALOG_QTY, }, }, { .type = ALPX_CONTROL_TYPE_AMPLIFIER, .base = ALP222_AES3_CAPTURE_AMPLI_BASE, .prefix = "AES Capture", .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_TLV_READ, .data.ampli = { .gains_scale = alpxxx_line_digital_gains_scale, .reg_gain_min = ALP_AMPLIFIER_GAIN_MIN_REG, .reg_gain_max = ALP_AMPLIFIER_GAIN_MAX_REG, .lines_count = ALP222_AES3_QTY, }, }, { .type = ALPX_CONTROL_TYPE_AMPLIFIER, .base = ALP222_DAW_PLAYBACK_AMPLI_BASE, .prefix = "DAW Playback", .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_TLV_READ, .data.ampli = { .gains_scale = alpxxx_line_digital_gains_scale, .reg_gain_min = ALP_AMPLIFIER_GAIN_MIN_REG, .reg_gain_max = ALP_AMPLIFIER_GAIN_MAX_REG, .lines_count = ALP222_DAW_QTY, }, }, /* OUTPUT Amplification*/ { .type = ALPX_CONTROL_TYPE_AMPLIFIER, .base = ALP222_ANALOG_PLAYBACK_AMPLI_BASE, .prefix = "Ana Playback", .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_TLV_READ, .data.ampli = { .gains_scale = alpxxx_line_digital_gains_scale, .reg_gain_min = ALP_AMPLIFIER_GAIN_MIN_REG, .reg_gain_max = ALP_AMPLIFIER_GAIN_MAX_REG, .lines_count = ALP222_ANALOG_QTY, }, }, { .type = ALPX_CONTROL_TYPE_AMPLIFIER, .base = ALP222_AES3_PLAYBACK_AMPLI_BASE, .prefix = "AES Playback", .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_TLV_READ, .data.ampli = { .gains_scale = alpxxx_line_digital_gains_scale, .reg_gain_min = ALP_AMPLIFIER_GAIN_MIN_REG, .reg_gain_max = ALP_AMPLIFIER_GAIN_MAX_REG, .lines_count = ALP222_AES3_QTY, }, }, { .type = ALPX_CONTROL_TYPE_AMPLIFIER, .base = ALP222_DAW_CAPTURE_AMPLI_BASE , .prefix = "DAW Capture", .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_TLV_READ, .data.ampli = { .gains_scale = alpxxx_line_digital_gains_scale, .reg_gain_min = ALP_AMPLIFIER_GAIN_MIN_REG, .reg_gain_max = ALP_AMPLIFIER_GAIN_MAX_REG, .lines_count = ALP222_DAW_QTY, }, }, /* Analog Eq */ { .type = ALPX_CONTROL_TYPE_ANALOG_EQ, .base = ALP222_CODEC_CTRL_BASE, .prefix = "Codec Analog Capture", .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_TLV_READ, .data.codec = { .offset = ALP222_CODEC_PGA_REGS, .gains_scale = alp222_line_analog_gains_scale, .reg_gain_min = ALP222_ANALOG_EQ_GAIN_MIN_REG, .reg_gain_max = ALP222_ANALOG_EQ_GAIN_MAX_REG, .lines_count = ALP222_ANALOG_QTY, }, }, /* Mixer */ { .type = ALPX_CONTROL_TYPE_MIXER, .base = ALP222_MIXER_BASE, .prefix = "Mxr", .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_TLV_READ, .data.mixer = { .lines_count = ALP222_MIXER_SIZE, .gains_scale = alpxxx_line_digital_gains_scale, .reg_gain_min = ALP_AMPLIFIER_GAIN_MIN_REG, .reg_gain_max = ALP_AMPLIFIER_GAIN_MAX_REG, }, }, /* Clock sources Read Only */ { .type = ALPX_CONTROL_TYPE_CHOICE, .base = ALP222_CLK_MANAGER_BASE, .prefix = "Clk Src", .access = SNDRV_CTL_ELEM_ACCESS_READ, .data.choice = { .offset = ALP222_CLK_MANAGER_CONFIG_REG, .mask = ALP222_CLK_MANAGER_CLK_SRC_MASK, .pos = ALP222_CLK_MANAGER_CLK_SRC_POS, .entries = alp222_control_choice_clk_src_entries, .entries_values = alp222_control_choice_clk_src_entries_values, .entries_count = ARRAY_SIZE(alp222_control_choice_clk_src_entries), }, }, /* Current Clock BASE Value Read Only */ { .type = ALPX_CONTROL_TYPE_CHOICE, .base = ALP222_CLK_MANAGER_BASE, .prefix = "Clk Eff", .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, .data.choice = { .offset = ALP222_CLK_MANAGER_CONFIG_REG, .mask = ALP222_CLK_MANAGER_CONFIG_CLK_CURRENT_VALUE_MASK, .pos = ALP222_CLK_MANAGER_CONFIG_CLK_CURRENT_VALUE_POS, .entries = alpxxx_control_choice_current_clk_values_entries, .entries_values = alpxxx_control_choice_current_clk_values_entries_values, .entries_count = ARRAY_SIZE(alpxxx_control_choice_current_clk_values_entries), }, }, /* Current Clock factor values Read Only RESERVED to keep id order */ { .type = ALPX_CONTROL_RESERVED, .base = ALP222_CLK_MANAGER_BASE, .prefix = "RESERVED", .access = SNDRV_CTL_ELEM_ACCESS_READ, }, /* AES SRC */ { .type = ALPX_CONTROL_TYPE_FLAG, .base = ALP222_CODEC_CTRL_BASE, .prefix = "AES SRC", .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, .data.flag = { .offset = ALP222_CODEC_CTRL_ASRC_REG, .mask = ALP222_CODEC_CTRL_ASRC_MASK, .pos = ALP222_CODEC_CTRL_ASRC_POS, }, }, /* Clock UP on fail over enabled flag */ { .type = ALPX_CONTROL_TYPE_FLAG, .base = ALP_PROC_BASE, .prefix = "CkSc Up", .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, .data.flag = { .offset = ALP_PROC_FWCONFIG_REG, .mask = ALP_PROC_FWCONFIG_CLKSRC_UP_MASK, .pos = ALP_PROC_FWCONFIG_CLKSRC_UP_POS, }, }, /* Clock DOWN on fail over enabled flag */ { .type = ALPX_CONTROL_TYPE_FLAG, .base = ALP_PROC_BASE, .prefix = "CkSc Down", .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, .data.flag = { .offset = ALP_PROC_FWCONFIG_REG, .mask = ALP_PROC_FWCONFIG_CLKSRC_DOWN_MASK, .pos = ALP_PROC_FWCONFIG_CLKSRC_DOWN_POS, }, }, /* Clock Failover priority 0 TOP*/ { .type = ALPX_CONTROL_TYPE_CHOICE, .base = ALP_PROC_BASE, .prefix = "Clk P0", .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, .data.choice = { .offset = ALP_PROC_CLK_SOURCE_PRIO_REG, .mask = ALP_PROC_CLK_SOURCE_PRIO0_MASK, .pos = ALP_PROC_CLK_SOURCE_PRIO0_POS, .entries = alp222_control_choice_clk_src_entries, .entries_values = alp222_control_choice_clk_src_entries_values, .entries_count = ARRAY_SIZE(alp222_control_choice_clk_src_entries), }, }, /* Clock Failover priority 1 */ { .type = ALPX_CONTROL_TYPE_CHOICE, .base = ALP_PROC_BASE, .prefix = "Clk P1", .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, .data.choice = { .offset = ALP_PROC_CLK_SOURCE_PRIO_REG, .mask = ALP_PROC_CLK_SOURCE_PRIO1_MASK, .pos = ALP_PROC_CLK_SOURCE_PRIO1_POS, .entries = alp222_control_choice_clk_src_entries, .entries_values = alp222_control_choice_clk_src_entries_values, .entries_count = ARRAY_SIZE(alp222_control_choice_clk_src_entries), }, }, /* Clock Failover priority 2*/ { .type = ALPX_CONTROL_TYPE_CHOICE, .base = ALP_PROC_BASE, .prefix = "Clk P2", .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, .data.choice = { .offset = ALP_PROC_CLK_SOURCE_PRIO_REG, .mask = ALP_PROC_CLK_SOURCE_PRIO2_MASK, .pos = ALP_PROC_CLK_SOURCE_PRIO2_POS, .entries = alp222_control_choice_clk_src_entries, .entries_values = alp222_control_choice_clk_src_entries_values, .entries_count = ARRAY_SIZE(alp222_control_choice_clk_src_entries), }, }, /* Clock Failover priority 3 Bottom*/ { .type = ALPX_CONTROL_TYPE_CHOICE, .base = ALP_PROC_BASE, .prefix = "Clk P3", .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, .data.choice = { .offset = ALP_PROC_CLK_SOURCE_PRIO_REG, .mask = ALP_PROC_CLK_SOURCE_PRIO3_MASK, .pos = ALP_PROC_CLK_SOURCE_PRIO3_POS, .entries = alp222_control_choice_clk_src_entries, .entries_values = alp222_control_choice_clk_src_entries_values, .entries_count = ARRAY_SIZE(alp222_control_choice_clk_src_entries), }, }, /* MIC INPUT Amplification (the gains MUST BE KEPT FIRST, control initialization)*/ { .type = ALPX_CONTROL_TYPE_GAINS_EMBEDDED, .base = ALP222_CONTROL_BASE, .prefix = "McGaL Capture", .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_TLV_READ, .data.mic_gains = { .min = ALP222_MIC_GAINS_MIN_REG_VAL, .max = ALP222_MIC_GAINS_MAX_REG_VAL, .lines_count = 1, /* Only one line per mic side on 222e*/ .offset = ALP222_MIC_CONTROL_REG, .mask = ALP222_MIC_GAIN_L_MASK, .pos = ALP222_MIC_GAIN_L_POS, .width = ALP222_MIC_GAIN_WIDTH, .gains_scale = alp222_mic_control_scale, }, }, { .type = ALPX_CONTROL_TYPE_GAINS_EMBEDDED, .base = ALP222_CONTROL_BASE, .prefix = "McGaR Capture", .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_TLV_READ, .data.mic_gains = { .min = ALP222_MIC_GAINS_MIN_REG_VAL, .max = ALP222_MIC_GAINS_MAX_REG_VAL, .lines_count = 1, /* Only one line per mic side on 222e*/ .offset = ALP222_MIC_CONTROL_REG, .mask = ALP222_MIC_GAIN_R_MASK, .pos = ALP222_MIC_GAIN_R_POS, .width = ALP222_MIC_GAIN_WIDTH, .gains_scale = alp222_mic_control_scale, }, }, /* MIC Phantom */ { .type = ALPX_CONTROL_TYPE_FLAGS_EMBEDDED, .base = ALP222_CONTROL_BASE, .prefix = "McPhL", .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, .data.mic_flags = { .offset = ALP222_MIC_CONTROL_REG, .mask = ALP222_MIC_PH_L_MASK, .pos = ALP222_MIC_PH_L_POS, .lines_count = 1, // Should be if control items[i] was Ok : ALP222_ANALOG_QTY, }, }, { .type = ALPX_CONTROL_TYPE_FLAGS_EMBEDDED, .base = ALP222_CONTROL_BASE, .prefix = "McPhR", .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, .data.mic_flags = { .offset = ALP222_MIC_CONTROL_REG, .mask = ALP222_MIC_PH_R_MASK, .pos = ALP222_MIC_PH_R_POS, .lines_count = 1, // Should be if control items[i] was Ok : ALP222_ANALOG_QTY, }, }, /* MIC Enable*/ { .type = ALPX_CONTROL_TYPE_FLAGS_EMBEDDED, .base = ALP222_CONTROL_BASE, .prefix = "McEnL", .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, .data.mic_flags = { .offset = ALP222_MIC_CONTROL_REG, .mask = ALP222_MIC_EN_L_MASK, .pos = ALP222_MIC_EN_L_POS, .lines_count = 1, // Should be if control items[i] was Ok : ALP222_ANALOG_QTY, }, }, { .type = ALPX_CONTROL_TYPE_FLAGS_EMBEDDED, .base = ALP222_CONTROL_BASE, .prefix = "McEnR", .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, .data.mic_flags = { .offset = ALP222_MIC_CONTROL_REG, .mask = ALP222_MIC_EN_R_MASK, .pos = ALP222_MIC_EN_R_POS, .lines_count = 1, // Should be if control items[i] was Ok : ALP222_ANALOG_QTY, }, }, }; static struct alpx_variant alp222_mic_variant __attribute__((unused)) = { .shortname = "Alp222e-MIC", .longname = "Alp 222e-MIC", .model = ALPX_VARIANT_MODEL_ALP222_MIC, .mixername = "Alp222e_MIC_Mix", .features = ALPX_VARIANT_FEATURE_GPIOS, .control_descriptors = alp222_mic_control_descriptors, .control_descriptors_count = ARRAY_SIZE(alp222_mic_control_descriptors), .capture_hw = &alp222_hardware_specs, .playback_hw = &alp222_hardware_specs, .flash_golden_production_base = ALPxxx_FLASH_GOLDEN_PRODUCTION_BASE, .gpios = { .base = ALP222_GPIO_BASE, .inputs_reg_offset = ALP222_GPIO_INPUT_REG, .inputs_qty = ALP222_GPIO_INPUT_QTY, .outputs_reg_offset = ALP222_GPIO_OUTPUT_REG, .outputs_qty = ALP222_GPIO_OUTPUT_QTY, }, .flash_partitions.partitions = alpx_mtd_partitions, .flash_partitions.qty = ARRAY_SIZE(alpx_mtd_partitions), .flash_partitions.qty_for_fw_update = 1, }; #endif /* _ALPX_VARIANTS_STEREO_H_ */