// SPDX-License-Identifier: GPL-2.0-or-later
/*
*  Support for Digigram AlpX PCI-e boards
*
*  Copyright (c) 2024 Digigram Digital (info@digigram.com)
*/

#ifndef _ALPX_VARIANTS_MC_H_
#define _ALPX_VARIANTS_MC_H_

#include "alpx.h"
#include "alpx_reg.h"

#include <sound/tlv.h>
#include "alpx_variants_common.h"


/* 882 */
/* Alp882 Commons */
static const char *alp882_control_choice_clk_src_entries[ALP882_CLK_MANAGER_CONFIG_CLK_SRC_QTY] = {
	"Internal",
	"SIC", 
	"Word Clk", 
	"AES Syn", 
	"AES Aud 1/2",
	"AES Aud 3/4", 
	"AES Aud 5/6", 
	"AES Aud 7/8", 
};

/* Same order than the constants values */
static u32 alp882_control_choice_clk_src_entries_values[ALP882_CLK_MANAGER_CONFIG_CLK_SRC_QTY] = {
	ALPMC_CLK_MANAGER_SOURCE_INTERNAL,
	ALPMC_CLK_MANAGER_SOURCE_SIC,
	ALPMC_CLK_MANAGER_SOURCE_WCLK_IN,
	ALPMC_CLK_MANAGER_SOURCE_AES_SYNC,
	ALPMC_CLK_MANAGER_SOURCE_AES_AUDIO_12,
	ALPMC_CLK_MANAGER_SOURCE_AES_AUDIO_34,
	ALPMC_CLK_MANAGER_SOURCE_AES_AUDIO_56,
	ALPMC_CLK_MANAGER_SOURCE_AES_AUDIO_78,
};

static struct snd_pcm_hardware alp882_hardware_specs = {
	.info			= SNDRV_PCM_INFO_MMAP |
				SNDRV_PCM_INFO_MMAP_VALID |
				SNDRV_PCM_INFO_INTERLEAVED |
				SNDRV_PCM_INFO_BLOCK_TRANSFER |
				SNDRV_PCM_INFO_RESUME,
	.formats		= SNDRV_PCM_FMTBIT_S32_LE,
	.rates			= SNDRV_PCM_RATE_CONTINUOUS |
				SNDRV_PCM_RATE_8000_192000,
	.rate_min		= 8000,
	.rate_max		= 192000,
	.channels_min		= 16,
	.channels_max		= 16,
	.buffer_bytes_max	= 256 * SZ_1K * 4, /* period_bytes_max * periods_max */
	.period_bytes_min   = 48, /* min latency 1ms */
	.period_bytes_max	= 256 * SZ_1K, /* 20ms at 192kHz * nchans * 4B, rounded at 2^n */
	.periods_min		= 1,
	.periods_max		= 4,
};


/* Alp 882 LINE Variant definition */

static const DECLARE_TLV_DB_MINMAX_MUTE(alpmc_line_control_codec_gains_scale, ALPMC_LINE_ANALOG_GAIN_MIN_cdB, ALPMC_LINE_ANALOG_GAIN_MAX_cdB);

static struct alpx_control_descriptor alp882_line_control_descriptors[] = {
	/* Gain */
	{
		.type			= ALPX_CONTROL_TYPE_AMPLIFIER,
		.base			= ALPMC_AMPLI_IN_BASE +
					ALPMC_GAIN_TABLE_BASE(ALP882_CHANNELS_IN_DAW_OFFSET),
		.prefix			= "DAW Capture",
		.access			= SNDRV_CTL_ELEM_ACCESS_READWRITE |
								SNDRV_CTL_ELEM_ACCESS_TLV_READ,
		.data.ampli = {
			.gains_scale = alpxxx_line_digital_gains_scale,
			.reg_gain_min	= ALP_AMPLIFIER_GAIN_MIN_REG,
			.reg_gain_max	= ALP_AMPLIFIER_GAIN_MAX_REG,
			.lines_count	= ALP882_CHANNELS_DAW_COUNT,
		},
	},
	{
		.type			= ALPX_CONTROL_TYPE_AMPLIFIER,
		.base			= ALPMC_AMPLI_IN_BASE +
					ALPMC_GAIN_TABLE_BASE(ALP882_CHANNELS_IN_ANALOG_OFFSET),
		.prefix			= "Ana Capture",
		.access			= SNDRV_CTL_ELEM_ACCESS_READWRITE |
								SNDRV_CTL_ELEM_ACCESS_TLV_READ,
		.data.ampli = {
			.gains_scale = alpxxx_line_digital_gains_scale,
			.reg_gain_min	= ALP_AMPLIFIER_GAIN_MIN_REG,
			.reg_gain_max	= ALP_AMPLIFIER_GAIN_MAX_REG,
			.lines_count	= ALP882_CHANNELS_ANALOG_COUNT,
		},
	},
	{
		.type			= ALPX_CONTROL_TYPE_AMPLIFIER,
		.base			= ALPMC_AMPLI_IN_BASE +
					ALPMC_GAIN_TABLE_BASE(ALP882_CHANNELS_IN_AES_OFFSET),
		.prefix			= "AES Capture",
		.access			= SNDRV_CTL_ELEM_ACCESS_READWRITE |
								SNDRV_CTL_ELEM_ACCESS_TLV_READ,
		.data.ampli = {
			.gains_scale = alpxxx_line_digital_gains_scale,
			.reg_gain_min	= ALP_AMPLIFIER_GAIN_MIN_REG,
			.reg_gain_max	= ALP_AMPLIFIER_GAIN_MAX_REG,
			.lines_count	= ALP882_CHANNELS_AES_COUNT,
		},
	},
	{
		.type			= ALPX_CONTROL_TYPE_AMPLIFIER,
		.base			= ALPMC_AMPLI_OUT_BASE +
					ALPMC_GAIN_TABLE_BASE(ALP882_CHANNELS_OUT_ANALOG_OFFSET),
		.prefix			= "Ana Playback",
		.access			= SNDRV_CTL_ELEM_ACCESS_READWRITE |
								SNDRV_CTL_ELEM_ACCESS_TLV_READ,
		.data.ampli = {
			.gains_scale = alpxxx_line_digital_gains_scale,
			.reg_gain_min	= ALP_AMPLIFIER_GAIN_MIN_REG,
			.reg_gain_max	= ALP_AMPLIFIER_GAIN_MAX_REG,
			.lines_count	= ALP882_CHANNELS_ANALOG_COUNT,
		},
	},
	{
		.type			= ALPX_CONTROL_TYPE_AMPLIFIER,
		.base			= ALPMC_AMPLI_OUT_BASE +
					ALPMC_GAIN_TABLE_BASE(ALP882_CHANNELS_OUT_AES_OFFSET),
		.prefix			= "AES Playback",
		.access			= SNDRV_CTL_ELEM_ACCESS_READWRITE |
								SNDRV_CTL_ELEM_ACCESS_TLV_READ,
		.data.ampli = {
			.gains_scale = alpxxx_line_digital_gains_scale,
			.reg_gain_min	= ALP_AMPLIFIER_GAIN_MIN_REG,
			.reg_gain_max	= ALP_AMPLIFIER_GAIN_MAX_REG,
			.lines_count	= ALP882_CHANNELS_AES_COUNT,
		},
	},
	{
		.type			= ALPX_CONTROL_TYPE_AMPLIFIER,
		.base			= ALPMC_AMPLI_OUT_BASE +
					ALPMC_GAIN_TABLE_BASE(ALP882_CHANNELS_OUT_DAW_OFFSET),
		.prefix			= "DAW Playback",
		.access			= SNDRV_CTL_ELEM_ACCESS_READWRITE |
								SNDRV_CTL_ELEM_ACCESS_TLV_READ,
		.data.ampli = {
			.gains_scale = alpxxx_line_digital_gains_scale,
			.reg_gain_min	= ALP_AMPLIFIER_GAIN_MIN_REG,
			.reg_gain_max	= ALP_AMPLIFIER_GAIN_MAX_REG,
			.lines_count	= ALP882_CHANNELS_DAW_COUNT,
		},
	},
		/* Mixer */
	{
		.type			= ALPX_CONTROL_TYPE_MIXER,
		.base			= ALPMC_MIXER_BASE,
		.prefix			= "Mxr",
		.access			= SNDRV_CTL_ELEM_ACCESS_READWRITE |
								SNDRV_CTL_ELEM_ACCESS_TLV_READ,
		.data.mixer		= {
			.lines_count	= ALP882_MIXER_SIZE,
			.gains_scale = alpxxx_line_digital_gains_scale,
			.reg_gain_min	= ALP_AMPLIFIER_GAIN_MIN_REG,
			.reg_gain_max	= ALP_AMPLIFIER_GAIN_MAX_REG,
		},
	},
	/* Clock sources Read Only */
	{
		.type			= ALPX_CONTROL_TYPE_CHOICE,
		.base			= ALPMC_CLK_MANAGER_BASE,
		.prefix			= "Clk Eff Src",
		.access			= SNDRV_CTL_ELEM_ACCESS_READ,
		.data.choice		= {
			.offset		= ALPMC_CLK_MANAGER_CONFIG_REG,
			.mask		= ALPMC_CLK_MANAGER_CONFIG_CLK_SRC_MASK,
			.pos = ALPMC_CLK_MANAGER_CONFIG_CLK_SRC_POS,
			.entries		= alp882_control_choice_clk_src_entries,
			.entries_values	= alp882_control_choice_clk_src_entries_values,
			.entries_count	= ARRAY_SIZE(alp882_control_choice_clk_src_entries),
		},
	},
	/* Current Clock BASE Value Read Only */
	{
		.type			= ALPX_CONTROL_TYPE_CHOICE,
		.base			= ALPMC_CLK_MANAGER_BASE,
		.prefix			= "Clk Eff",
		.access			= SNDRV_CTL_ELEM_ACCESS_READ | 
								SNDRV_CTL_ELEM_ACCESS_VOLATILE,
		.data.choice		= {
			.offset		= ALPMC_CLK_MANAGER_CONFIG_REG,
			.mask		= ALPMC_CLK_MANAGER_CONFIG_CLK_CURRENT_VALUE_MASK,
			.pos = ALPMC_CLK_MANAGER_CONFIG_CLK_CURRENT_VALUE_POS,
			.entries		= alpxxx_control_choice_current_clk_values_entries,
			.entries_values	= alpxxx_control_choice_current_clk_values_entries_values,
			.entries_count	= ARRAY_SIZE(alpxxx_control_choice_current_clk_values_entries),
		},
	},
	
	/* Current Clock factor values Read Only, RESERVED to keep Ids order */
	{
		.type			= ALPX_CONTROL_RESERVED,
		.base			= ALPMC_CLK_MANAGER_BASE,
		.prefix			= "RESERVED",
		.access			= SNDRV_CTL_ELEM_ACCESS_READ,
	},
		/* Clock UP on fail over enabled flag */
	{
		.type			= ALPX_CONTROL_TYPE_FLAG,
		.base			= ALP_PROC_BASE,
		.prefix			= "Clk Src Up",
		.access			= SNDRV_CTL_ELEM_ACCESS_READWRITE,
		.data.flag		= {
			.offset		= ALP_PROC_FWCONFIG_REG,
			.mask		= ALP_PROC_FWCONFIG_CLKSRC_UP_MASK,
			.pos		= ALP_PROC_FWCONFIG_CLKSRC_UP_POS,
		},
	},
	/* Clock DOWN on fail over enabled flag */
	{
		.type			= ALPX_CONTROL_TYPE_FLAG,
		.base			= ALP_PROC_BASE,
		.prefix			= "Clk Src Down",
		.access			= SNDRV_CTL_ELEM_ACCESS_READWRITE,
		.data.flag		= {
			.offset		= ALP_PROC_FWCONFIG_REG,
			.mask		= ALP_PROC_FWCONFIG_CLKSRC_DOWN_MASK,
			.pos		= ALP_PROC_FWCONFIG_CLKSRC_DOWN_POS,
		},
	},
	/* Clock Failover priority 0 TOP*/
	{
		.type			= ALPX_CONTROL_TYPE_CHOICE,
		.base			= ALP_PROC_BASE,
		.prefix			= "Clk P0",
		.access			= SNDRV_CTL_ELEM_ACCESS_READWRITE,
		.data.choice		= {
			.offset		= ALP_PROC_CLK_SOURCE_PRIO_REG,
			.mask		= ALP_PROC_CLK_SOURCE_PRIO0_MASK,
			.pos			= ALP_PROC_CLK_SOURCE_PRIO0_POS,
			.entries		= alp882_control_choice_clk_src_entries,
			.entries_values	= alp882_control_choice_clk_src_entries_values,
			.entries_count	= ARRAY_SIZE(alp882_control_choice_clk_src_entries),
		},
	},
	/* Clock Failover priority 1 */
	{
		.type			= ALPX_CONTROL_TYPE_CHOICE,
		.base			= ALP_PROC_BASE,
		.prefix			= "Clk P1",
		.access			= SNDRV_CTL_ELEM_ACCESS_READWRITE,
		.data.choice		= {
			.offset		= ALP_PROC_CLK_SOURCE_PRIO_REG,
			.mask		= ALP_PROC_CLK_SOURCE_PRIO1_MASK,
			.pos			= ALP_PROC_CLK_SOURCE_PRIO1_POS,
			.entries		= alp882_control_choice_clk_src_entries,
			.entries_values	= alp882_control_choice_clk_src_entries_values,
			.entries_count	= ARRAY_SIZE(alp882_control_choice_clk_src_entries),
		},
	},
	/* Clock Failover priority 2*/
	{
		.type			= ALPX_CONTROL_TYPE_CHOICE,
		.base			= ALP_PROC_BASE,
		.prefix			= "Clk P2",
		.access			= SNDRV_CTL_ELEM_ACCESS_READWRITE,
		.data.choice		= {
			.offset		= ALP_PROC_CLK_SOURCE_PRIO_REG,
			.mask		= ALP_PROC_CLK_SOURCE_PRIO2_MASK,
			.pos			= ALP_PROC_CLK_SOURCE_PRIO2_POS,
			.entries		= alp882_control_choice_clk_src_entries,
			.entries_values	= alp882_control_choice_clk_src_entries_values,
			.entries_count	= ARRAY_SIZE(alp882_control_choice_clk_src_entries),
		},
	},
	/* Clock Failover priority 3*/
	{
		.type			= ALPX_CONTROL_TYPE_CHOICE,
		.base			= ALP_PROC_BASE,
		.prefix			= "Clk P3",
		.access			= SNDRV_CTL_ELEM_ACCESS_READWRITE,
		.data.choice		= {
			.offset		= ALP_PROC_CLK_SOURCE_PRIO_REG,
			.mask		= ALP_PROC_CLK_SOURCE_PRIO3_MASK,
			.pos			= ALP_PROC_CLK_SOURCE_PRIO3_POS,
			.entries		= alp882_control_choice_clk_src_entries,
			.entries_values	= alp882_control_choice_clk_src_entries_values,
			.entries_count	= ARRAY_SIZE(alp882_control_choice_clk_src_entries),
		},
	},
	/* Auto AES SRC disable */
	{
		.type			= ALPX_CONTROL_TYPE_FLAG,
		.base			= ALPMC_CODEC_CTRL_BASE,
		.prefix			= "AES SRC 1/2 Disable",
		.access			= SNDRV_CTL_ELEM_ACCESS_READWRITE,
		.data.flag		= {
			.offset		= ALPMC_CODEC_AES_SRC_CONTROL_REG,
			.mask		= ALPMC_CODEC_AES_SRC_1_2_MASK,
			.pos			= ALPMC_CODEC_AES_SRC_1_2_POS,
		},
	},
	{
		.type			= ALPX_CONTROL_TYPE_FLAG,
		.base			= ALPMC_CODEC_CTRL_BASE,
		.prefix			= "AES SRC 3/4 Disable",
		.access			= SNDRV_CTL_ELEM_ACCESS_READWRITE,
		.data.flag		= {
			.offset		= ALPMC_CODEC_AES_SRC_CONTROL_REG,
			.mask		= ALPMC_CODEC_AES_SRC_3_4_MASK,
			.pos			= ALPMC_CODEC_AES_SRC_3_4_POS,
		},
	},
	{
		.type			= ALPX_CONTROL_TYPE_FLAG,
		.base			= ALPMC_CODEC_CTRL_BASE,
		.prefix			= "AES SRC 5/6 Disable",
		.access			= SNDRV_CTL_ELEM_ACCESS_READWRITE,
		.data.flag		= {
			.offset		= ALPMC_CODEC_AES_SRC_CONTROL_REG,
			.mask		= ALPMC_CODEC_AES_SRC_5_6_MASK,
			.pos			= ALPMC_CODEC_AES_SRC_5_6_POS,
		},
	},
	{
		.type			= ALPX_CONTROL_TYPE_FLAG,
		.base			= ALPMC_CODEC_CTRL_BASE,
		.prefix			= "AES SRC 7/8  Disable",
		.access			= SNDRV_CTL_ELEM_ACCESS_READWRITE,
		.data.flag		= {
			.offset		= ALPMC_CODEC_AES_SRC_CONTROL_REG,
			.mask		= ALPMC_CODEC_AES_SRC_7_8_MASK,
			.pos			= ALPMC_CODEC_AES_SRC_7_8_POS,
		},
	},
	/* Codec Input Gain for LINE Option*/
	{
		.type			= ALPX_CONTROL_TYPE_ANALOG_EQ,
		.base			= ALPMC_CODEC_CTRL_BASE,
		.prefix			= "Codec Analog Capture",
		.access			= SNDRV_CTL_ELEM_ACCESS_READWRITE |
								SNDRV_CTL_ELEM_ACCESS_TLV_READ,
		.data.codec		= {
			.offset = ALPMC_CODEC_PGA_REGS,
			.gains_scale = alpmc_line_control_codec_gains_scale,
			.reg_gain_min	= ALPMC_LINE_ANALOG_GAIN_MIN_REG,
			.reg_gain_max	= ALPMC_LINE_ANALOG_GAIN_MAX_REG,
			.lines_count	= 8,
		},
	},
};

static struct alpx_variant alp882_line_variant __attribute__((unused)) = {
	.shortname			= "Alp882e",
	.longname			= "Alp 882e",
	.model				= ALPX_VARIANT_MODEL_ALP882,
	.mixername			= "Alp882e_Mix",
	.features			= ALPX_VARIANT_FEATURE_GPIOS,
	.control_descriptors		= alp882_line_control_descriptors,
	.control_descriptors_count	= ARRAY_SIZE(alp882_line_control_descriptors),

	.capture_hw			= &alp882_hardware_specs,
	.playback_hw			= &alp882_hardware_specs,
	
	.flash_golden_production_base = ALPxxx_FLASH_GOLDEN_PRODUCTION_BASE,
	
	.gpios = {
	.base = ALPMC_GPIO_BASE,
	.inputs_reg_offset = ALPMC_GPIO_INPUT_REG,
	.inputs_qty = ALPMC_GPIO_INPUT_QTY,
	.outputs_reg_offset = ALPMC_GPIO_OUTPUT_REG,
	.outputs_qty = ALPMC_GPIO_OUTPUT_QTY,
	},
	
	.flash_partitions.partitions = alpx_mtd_partitions,
	.flash_partitions.qty = ARRAY_SIZE(alpx_mtd_partitions),
	.flash_partitions.qty_for_fw_update = 1,
};


/* Alp 882 - MIC  Variant definition */

static const DECLARE_TLV_DB_MINMAX_MUTE(alpmc_mic_control_codec_gains_scale, ALPMC_MIC_ANALOG_GAIN_MIN_cdB, ALPMC_MIC_ANALOG_GAIN_MAX_cdB);

static struct alpx_control_descriptor alp882_mic_control_descriptors[] = {
	/* Gain */
	{
		.type			= ALPX_CONTROL_TYPE_AMPLIFIER,
		.base			= ALPMC_AMPLI_IN_BASE +
					ALPMC_GAIN_TABLE_BASE(ALP882_CHANNELS_IN_DAW_OFFSET),
		.prefix			= "DAW Capture",
		.access			= SNDRV_CTL_ELEM_ACCESS_READWRITE |
								SNDRV_CTL_ELEM_ACCESS_TLV_READ,
		.data.ampli = {
			.gains_scale = alpxxx_line_digital_gains_scale,
			.reg_gain_min	= ALP_AMPLIFIER_GAIN_MIN_REG,
			.reg_gain_max	= ALP_AMPLIFIER_GAIN_MAX_REG,
			.lines_count	= ALP882_CHANNELS_DAW_COUNT,
		},
	},
	{
		.type			= ALPX_CONTROL_TYPE_AMPLIFIER,
		.base			= ALPMC_AMPLI_IN_BASE +
					ALPMC_GAIN_TABLE_BASE(ALP882_CHANNELS_IN_ANALOG_OFFSET),
		.prefix			= "Ana Capture",
		.access			= SNDRV_CTL_ELEM_ACCESS_READWRITE |
								SNDRV_CTL_ELEM_ACCESS_TLV_READ,
		.data.ampli = {
			.gains_scale = alpxxx_line_digital_gains_scale,
			.reg_gain_min	= ALP_AMPLIFIER_GAIN_MIN_REG,
			.reg_gain_max	= ALP_AMPLIFIER_GAIN_MAX_REG,
			.lines_count	= ALP882_CHANNELS_ANALOG_COUNT,
		},
	},
	{
		.type			= ALPX_CONTROL_TYPE_AMPLIFIER,
		.base			= ALPMC_AMPLI_IN_BASE +
					ALPMC_GAIN_TABLE_BASE(ALP882_CHANNELS_IN_AES_OFFSET),
		.prefix			= "AES Capture",
		.access			= SNDRV_CTL_ELEM_ACCESS_READWRITE |
								SNDRV_CTL_ELEM_ACCESS_TLV_READ,
		.data.ampli = {
			.gains_scale = alpxxx_line_digital_gains_scale,
			.reg_gain_min	= ALP_AMPLIFIER_GAIN_MIN_REG,
			.reg_gain_max	= ALP_AMPLIFIER_GAIN_MAX_REG,
			.lines_count	= ALP882_CHANNELS_AES_COUNT,
		},
	},
	{
		.type			= ALPX_CONTROL_TYPE_AMPLIFIER,
		.base			= ALPMC_AMPLI_OUT_BASE +
					ALPMC_GAIN_TABLE_BASE(ALP882_CHANNELS_OUT_ANALOG_OFFSET),
		.prefix			= "Ana Playback",
		.access			= SNDRV_CTL_ELEM_ACCESS_READWRITE |
								SNDRV_CTL_ELEM_ACCESS_TLV_READ,
		.data.ampli = {
			.gains_scale = alpxxx_line_digital_gains_scale,
			.reg_gain_min	= ALP_AMPLIFIER_GAIN_MIN_REG,
			.reg_gain_max	= ALP_AMPLIFIER_GAIN_MAX_REG,
			.lines_count	= ALP882_CHANNELS_ANALOG_COUNT,
		},
	},
	{
		.type			= ALPX_CONTROL_TYPE_AMPLIFIER,
		.base			= ALPMC_AMPLI_OUT_BASE +
					ALPMC_GAIN_TABLE_BASE(ALP882_CHANNELS_OUT_AES_OFFSET),
		.prefix			= "AES Playback",
		.access			= SNDRV_CTL_ELEM_ACCESS_READWRITE |
								SNDRV_CTL_ELEM_ACCESS_TLV_READ,
		.data.ampli = {
			.gains_scale = alpxxx_line_digital_gains_scale,
			.reg_gain_min	= ALP_AMPLIFIER_GAIN_MIN_REG,
			.reg_gain_max	= ALP_AMPLIFIER_GAIN_MAX_REG,
			.lines_count	= ALP882_CHANNELS_AES_COUNT,
		},
	},
	{
		.type			= ALPX_CONTROL_TYPE_AMPLIFIER,
		.base			= ALPMC_AMPLI_OUT_BASE +
					ALPMC_GAIN_TABLE_BASE(ALP882_CHANNELS_OUT_DAW_OFFSET),
		.prefix			= "DAW Playback",
		.access			= SNDRV_CTL_ELEM_ACCESS_READWRITE |
								SNDRV_CTL_ELEM_ACCESS_TLV_READ,
		.data.ampli = {
			.gains_scale = alpxxx_line_digital_gains_scale,
			.reg_gain_min	= ALP_AMPLIFIER_GAIN_MIN_REG,
			.reg_gain_max	= ALP_AMPLIFIER_GAIN_MAX_REG,
			.lines_count	= ALP882_CHANNELS_DAW_COUNT,
		},
	},
		/* Mixer */
	{
		.type			= ALPX_CONTROL_TYPE_MIXER,
		.base			= ALPMC_MIXER_BASE,
		.prefix			= "Mxr",
		.access			= SNDRV_CTL_ELEM_ACCESS_READWRITE |
								SNDRV_CTL_ELEM_ACCESS_TLV_READ,
		.data.mixer		= {
			.lines_count	= ALP882_MIXER_SIZE,
			.gains_scale = alpxxx_line_digital_gains_scale,
			.reg_gain_min	= ALP_AMPLIFIER_GAIN_MIN_REG,
			.reg_gain_max	= ALP_AMPLIFIER_GAIN_MAX_REG,
		},
	},
	/* Clock sources Read Only */
	{
		.type			= ALPX_CONTROL_TYPE_CHOICE,
		.base			= ALPMC_CLK_MANAGER_BASE,
		.prefix			= "Clk Eff Src",
		.access			= SNDRV_CTL_ELEM_ACCESS_READ,
		.data.choice		= {
			.offset		= ALPMC_CLK_MANAGER_CONFIG_REG,
			.mask		= ALPMC_CLK_MANAGER_CONFIG_CLK_SRC_MASK,
			.pos = ALPMC_CLK_MANAGER_CONFIG_CLK_SRC_POS,
			.entries		= alp882_control_choice_clk_src_entries,
			.entries_values	= alp882_control_choice_clk_src_entries_values,
			.entries_count	= ARRAY_SIZE(alp882_control_choice_clk_src_entries),
		},
	},
	/* Current Clock BASE Value Read Only */
	{
		.type			= ALPX_CONTROL_TYPE_CHOICE,
		.base			= ALPMC_CLK_MANAGER_BASE,
		.prefix			= "Clk Eff",
		.access			= SNDRV_CTL_ELEM_ACCESS_READ | 
								SNDRV_CTL_ELEM_ACCESS_VOLATILE,
		.data.choice		= {
			.offset		= ALPMC_CLK_MANAGER_CONFIG_REG,
			.mask		= ALPMC_CLK_MANAGER_CONFIG_CLK_CURRENT_VALUE_MASK,
			.pos = ALPMC_CLK_MANAGER_CONFIG_CLK_CURRENT_VALUE_POS,
			.entries		= alpxxx_control_choice_current_clk_values_entries,
			.entries_values	= alpxxx_control_choice_current_clk_values_entries_values,
			.entries_count	= ARRAY_SIZE(alpxxx_control_choice_current_clk_values_entries),
		},
	},
	
	/* Current Clock factor values Read Only, RESERVED now to keep ids order */
	{
		.type			= ALPX_CONTROL_RESERVED,
		.base			= ALPMC_CLK_MANAGER_BASE,
		.prefix			= "RESERVED",
		.access			= SNDRV_CTL_ELEM_ACCESS_READ,
	},
		/* Clock UP on fail over enabled flag */
	{
		.type			= ALPX_CONTROL_TYPE_FLAG,
		.base			= ALP_PROC_BASE,
		.prefix			= "Clk Src Up",
		.access			= SNDRV_CTL_ELEM_ACCESS_READWRITE,
		.data.flag		= {
			.offset		= ALP_PROC_FWCONFIG_REG,
			.mask		= ALP_PROC_FWCONFIG_CLKSRC_UP_MASK,
			.pos		= ALP_PROC_FWCONFIG_CLKSRC_UP_POS,
		},
	},
	/* Clock DOWN on fail over enabled flag */
	{
		.type			= ALPX_CONTROL_TYPE_FLAG,
		.base			= ALP_PROC_BASE,
		.prefix			= "Clk Src Down",
		.access			= SNDRV_CTL_ELEM_ACCESS_READWRITE,
		.data.flag		= {
			.offset		= ALP_PROC_FWCONFIG_REG,
			.mask		= ALP_PROC_FWCONFIG_CLKSRC_DOWN_MASK,
			.pos		= ALP_PROC_FWCONFIG_CLKSRC_DOWN_POS,
		},
	},
	/* Clock Failover priority 0 TOP*/
	{
		.type			= ALPX_CONTROL_TYPE_CHOICE,
		.base			= ALP_PROC_BASE,
		.prefix			= "Clk P0",
		.access			= SNDRV_CTL_ELEM_ACCESS_READWRITE,
		.data.choice		= {
			.offset		= ALP_PROC_CLK_SOURCE_PRIO_REG,
			.mask		= ALP_PROC_CLK_SOURCE_PRIO0_MASK,
			.pos			= ALP_PROC_CLK_SOURCE_PRIO0_POS,
			.entries		= alp882_control_choice_clk_src_entries,
			.entries_values	= alp882_control_choice_clk_src_entries_values,
			.entries_count	= ARRAY_SIZE(alp882_control_choice_clk_src_entries),
		},
	},
	/* Clock Failover priority 1 */
	{
		.type			= ALPX_CONTROL_TYPE_CHOICE,
		.base			= ALP_PROC_BASE,
		.prefix			= "Clk P1",
		.access			= SNDRV_CTL_ELEM_ACCESS_READWRITE,
		.data.choice		= {
			.offset		= ALP_PROC_CLK_SOURCE_PRIO_REG,
			.mask		= ALP_PROC_CLK_SOURCE_PRIO1_MASK,
			.pos			= ALP_PROC_CLK_SOURCE_PRIO1_POS,
			.entries		= alp882_control_choice_clk_src_entries,
			.entries_values	= alp882_control_choice_clk_src_entries_values,
			.entries_count	= ARRAY_SIZE(alp882_control_choice_clk_src_entries),
		},
	},
	/* Clock Failover priority 2*/
	{
		.type			= ALPX_CONTROL_TYPE_CHOICE,
		.base			= ALP_PROC_BASE,
		.prefix			= "Clk P2",
		.access			= SNDRV_CTL_ELEM_ACCESS_READWRITE,
		.data.choice		= {
			.offset		= ALP_PROC_CLK_SOURCE_PRIO_REG,
			.mask		= ALP_PROC_CLK_SOURCE_PRIO2_MASK,
			.pos			= ALP_PROC_CLK_SOURCE_PRIO2_POS,
			.entries		= alp882_control_choice_clk_src_entries,
			.entries_values	= alp882_control_choice_clk_src_entries_values,
			.entries_count	= ARRAY_SIZE(alp882_control_choice_clk_src_entries),
		},
	},
	/* Clock Failover priority 3*/
	{
		.type			= ALPX_CONTROL_TYPE_CHOICE,
		.base			= ALP_PROC_BASE,
		.prefix			= "Clk P3",
		.access			= SNDRV_CTL_ELEM_ACCESS_READWRITE,
		.data.choice		= {
			.offset		= ALP_PROC_CLK_SOURCE_PRIO_REG,
			.mask		= ALP_PROC_CLK_SOURCE_PRIO3_MASK,
			.pos			= ALP_PROC_CLK_SOURCE_PRIO3_POS,
			.entries		= alp882_control_choice_clk_src_entries,
			.entries_values	= alp882_control_choice_clk_src_entries_values,
			.entries_count	= ARRAY_SIZE(alp882_control_choice_clk_src_entries),
		},
	},
	/* Auto AES SRC disable */
	{
		.type			= ALPX_CONTROL_TYPE_FLAG,
		.base			= ALPMC_CODEC_CTRL_BASE,
		.prefix			= "AES SRC 1/2 Disable",
		.access			= SNDRV_CTL_ELEM_ACCESS_READWRITE,
		.data.flag		= {
			.offset		= ALPMC_CODEC_AES_SRC_CONTROL_REG,
			.mask		= ALPMC_CODEC_AES_SRC_1_2_MASK,
			.pos			= ALPMC_CODEC_AES_SRC_1_2_POS,
		},
	},
	{
		.type			= ALPX_CONTROL_TYPE_FLAG,
		.base			= ALPMC_CODEC_CTRL_BASE,
		.prefix			= "AES SRC 3/4 Disable",
		.access			= SNDRV_CTL_ELEM_ACCESS_READWRITE,
		.data.flag		= {
			.offset		= ALPMC_CODEC_AES_SRC_CONTROL_REG,
			.mask		= ALPMC_CODEC_AES_SRC_3_4_MASK,
			.pos			= ALPMC_CODEC_AES_SRC_3_4_POS,
		},
	},
	{
		.type			= ALPX_CONTROL_TYPE_FLAG,
		.base			= ALPMC_CODEC_CTRL_BASE,
		.prefix			= "AES SRC 5/6 Disable",
		.access			= SNDRV_CTL_ELEM_ACCESS_READWRITE,
		.data.flag		= {
			.offset		= ALPMC_CODEC_AES_SRC_CONTROL_REG,
			.mask		= ALPMC_CODEC_AES_SRC_5_6_MASK,
			.pos			= ALPMC_CODEC_AES_SRC_5_6_POS,
		},
	},
	{
		.type			= ALPX_CONTROL_TYPE_FLAG,
		.base			= ALPMC_CODEC_CTRL_BASE,
		.prefix			= "AES SRC 7/8  Disable",
		.access			= SNDRV_CTL_ELEM_ACCESS_READWRITE,
		.data.flag		= {
			.offset		= ALPMC_CODEC_AES_SRC_CONTROL_REG,
			.mask		= ALPMC_CODEC_AES_SRC_7_8_MASK,
			.pos			= ALPMC_CODEC_AES_SRC_7_8_POS,
		},
	},
	/* Codec Input Gain for MIC Option*/
	{
		.type			= ALPX_CONTROL_TYPE_ANALOG_EQ,
		.base			= ALPMC_CODEC_CTRL_BASE,
		.prefix			= "Codec MIC Analog Capture",
		.access			= SNDRV_CTL_ELEM_ACCESS_READWRITE |
								SNDRV_CTL_ELEM_ACCESS_TLV_READ,
		.data.codec		= {
			.offset = ALPMC_CODEC_PGA_REGS,
			.gains_scale = alpmc_mic_control_codec_gains_scale,
			.reg_gain_min	= ALPMC_MIC_ANALOG_GAIN_MIN_REG,
			.reg_gain_max	= ALPMC_MIC_ANALOG_GAIN_MAX_REG,
			.lines_count	= 8,
		},
	},
		/** MIC Phantoms **/
	/* MIC Phantom 1 */
	{
		.type			= ALPX_CONTROL_TYPE_FLAG,
		.base			= ALPMC_CODEC_CTRL_BASE,
		.prefix			= "McPh1",
		.access			= SNDRV_CTL_ELEM_ACCESS_READWRITE,
		.data.mic_flags		= {
			.offset		= ALPMC_INPUT_PARAMS_REG,
			.mask		= ALPMC_MIC_INPUT_PH_1_MASK,
			.pos		= ALPMC_MIC_INPUT_PH_1_POS,
		},
	},
	/* MIC Phantom 2 */
	{
		.type			= ALPX_CONTROL_TYPE_FLAG,
		.base			= ALPMC_CODEC_CTRL_BASE,
		.prefix			= "McPh2",
		.access			= SNDRV_CTL_ELEM_ACCESS_READWRITE,
		.data.mic_flags		= {
			.offset		= ALPMC_INPUT_PARAMS_REG,
			.mask		= ALPMC_MIC_INPUT_PH_2_MASK,
			.pos		= ALPMC_MIC_INPUT_PH_2_POS,
		},
	},
	/* MIC Phantom 3 */
	{
		.type			= ALPX_CONTROL_TYPE_FLAG,
		.base			= ALPMC_CODEC_CTRL_BASE,
		.prefix			= "McPh3",
		.access			= SNDRV_CTL_ELEM_ACCESS_READWRITE,
		.data.mic_flags		= {
			.offset		= ALPMC_INPUT_PARAMS_REG,
			.mask		= ALPMC_MIC_INPUT_PH_3_MASK,
			.pos		= ALPMC_MIC_INPUT_PH_3_POS,
		},
	},
	/* MIC Phantom 4 */
	{
		.type			= ALPX_CONTROL_TYPE_FLAG,
		.base			= ALPMC_CODEC_CTRL_BASE,
		.prefix			= "McPh4",
		.access			= SNDRV_CTL_ELEM_ACCESS_READWRITE,
		.data.mic_flags		= {
			.offset		= ALPMC_INPUT_PARAMS_REG,
			.mask		= ALPMC_MIC_INPUT_PH_4_MASK,
			.pos			= ALPMC_MIC_INPUT_PH_4_POS,
		},
	},
	/* MIC Phantom 5 */
	{
		.type			= ALPX_CONTROL_TYPE_FLAG,
		.base			= ALPMC_CODEC_CTRL_BASE,
		.prefix			= "McPh5",
		.access			= SNDRV_CTL_ELEM_ACCESS_READWRITE,
		.data.mic_flags		= {
			.offset		= ALPMC_INPUT_PARAMS_REG,
			.mask		= ALPMC_MIC_INPUT_PH_5_MASK,
			.pos			= ALPMC_MIC_INPUT_PH_5_POS,
		},
	},
	/* MIC Phantom 6 */
	{
		.type			= ALPX_CONTROL_TYPE_FLAG,
		.base			= ALPMC_CODEC_CTRL_BASE,
		.prefix			= "McPh6",
		.access			= SNDRV_CTL_ELEM_ACCESS_READWRITE,
		.data.mic_flags		= {
			.offset		= ALPMC_INPUT_PARAMS_REG,
			.mask		= ALPMC_MIC_INPUT_PH_6_MASK,
			.pos			= ALPMC_MIC_INPUT_PH_6_POS,
		},
	},
	/* MIC Phantom 7 */
	{
		.type			= ALPX_CONTROL_TYPE_FLAG,
		.base			= ALPMC_CODEC_CTRL_BASE,
		.prefix			= "McPh7",
		.access			= SNDRV_CTL_ELEM_ACCESS_READWRITE,
		.data.mic_flags		= {
			.offset		= ALPMC_INPUT_PARAMS_REG,
			.mask		= ALPMC_MIC_INPUT_PH_7_MASK,
			.pos			= ALPMC_MIC_INPUT_PH_7_POS,
		},
	},
	/* MIC Phantom 8 */
	{
		.type			= ALPX_CONTROL_TYPE_FLAG,
		.base			= ALPMC_CODEC_CTRL_BASE,
		.prefix			= "McPh8",
		.access			= SNDRV_CTL_ELEM_ACCESS_READWRITE,
		.data.mic_flags		= {
			.offset		= ALPMC_INPUT_PARAMS_REG,
			.mask		= ALPMC_MIC_INPUT_PH_8_MASK,
			.pos			= ALPMC_MIC_INPUT_PH_8_POS,
		},
	},
};


static struct alpx_variant alp882_mic_variant __attribute__((unused)) = {
	.shortname			= "Alp882e-MIC",
	.longname			= "Alp 882e MIC",
	.model				= ALPX_VARIANT_MODEL_ALP882_MIC,
	.mixername			= "Alp882e_MIC_Mix",
	.features			= ALPX_VARIANT_FEATURE_GPIOS,
	.control_descriptors		= alp882_mic_control_descriptors,
	.control_descriptors_count	= ARRAY_SIZE(alp882_mic_control_descriptors),

	.capture_hw			= &alp882_hardware_specs,
	.playback_hw			= &alp882_hardware_specs,
	
	.flash_golden_production_base = ALPxxx_FLASH_GOLDEN_PRODUCTION_BASE,
	
	.gpios = {
	.base = ALPMC_GPIO_BASE,
	.inputs_reg_offset = ALPMC_GPIO_INPUT_REG,
	.inputs_qty = ALPMC_GPIO_INPUT_QTY,
	.outputs_reg_offset = ALPMC_GPIO_OUTPUT_REG,
	.outputs_qty = ALPMC_GPIO_OUTPUT_QTY,
	},
	
	.flash_partitions.partitions = alpx_mtd_partitions,
	.flash_partitions.qty = ARRAY_SIZE(alpx_mtd_partitions),
	.flash_partitions.qty_for_fw_update = 1,
};

/* 442 */
/* Commons clock sources : WARNING : Sme as 882 for the moment */
static const char *alp442_control_choice_clk_src_entries[ALP442_CLK_MANAGER_CONFIG_CLK_SRC_QTY] = {
	"Internal",
	"SIC",
	"Word Clk", 
	"AES Syn", 
	"AES Aud 1/2",
	"AES Aud 3/4",
};

/* Same order than the constants values */
static u32 alp442_control_choice_clk_src_entries_values[ALP442_CLK_MANAGER_CONFIG_CLK_SRC_QTY] = {
	ALPMC_CLK_MANAGER_SOURCE_INTERNAL,
	ALPMC_CLK_MANAGER_SOURCE_SIC,
	ALPMC_CLK_MANAGER_SOURCE_WCLK_IN,
	ALPMC_CLK_MANAGER_SOURCE_AES_SYNC,
	ALPMC_CLK_MANAGER_SOURCE_AES_AUDIO_12,
	ALPMC_CLK_MANAGER_SOURCE_AES_AUDIO_34
};

static struct snd_pcm_hardware alp442_hardware_specs = {
	.info			= SNDRV_PCM_INFO_MMAP |
				SNDRV_PCM_INFO_MMAP_VALID |
				SNDRV_PCM_INFO_INTERLEAVED |
				SNDRV_PCM_INFO_BLOCK_TRANSFER |
				SNDRV_PCM_INFO_RESUME,
	.formats		= SNDRV_PCM_FMTBIT_S32_LE,
	.rates			= SNDRV_PCM_RATE_CONTINUOUS |
				SNDRV_PCM_RATE_8000_192000,
	.rate_min		= 8000,
	.rate_max		= 192000,
	.channels_min		= ALP442_CHANNELS_DAW_COUNT,
	.channels_max		= ALP442_CHANNELS_DAW_COUNT,
	.buffer_bytes_max	= 128 * SZ_1K * 4, /* period_bytes_max * periods_max */
	.period_bytes_min   = 48, /* min latency 1ms */
	.period_bytes_max	= 128 * SZ_1K, /* 20ms at 192kHz * nchans * 4B, rounded at 2^n */
	.periods_min		= 1,
	.periods_max		= 4,
};


/* Alp 442 LINE Variant definition */


static struct alpx_control_descriptor alp442_line_control_descriptors[] = {
	/* Gain */
	{
		.type			= ALPX_CONTROL_TYPE_AMPLIFIER,
		.base			= ALPMC_AMPLI_IN_BASE +
					ALPMC_GAIN_TABLE_BASE(ALP442_CHANNELS_IN_DAW_OFFSET),
		.prefix			= "DAW Capture",
		.access			= SNDRV_CTL_ELEM_ACCESS_READWRITE |
								SNDRV_CTL_ELEM_ACCESS_TLV_READ,
		.data.ampli = {
			.gains_scale = alpxxx_line_digital_gains_scale,
			.reg_gain_min	= ALP_AMPLIFIER_GAIN_MIN_REG,
			.reg_gain_max	= ALP_AMPLIFIER_GAIN_MAX_REG,
			.lines_count	= ALP442_CHANNELS_DAW_COUNT,
		},
	},
	{
		.type			= ALPX_CONTROL_TYPE_AMPLIFIER,
		.base			= ALPMC_AMPLI_IN_BASE +
					ALPMC_GAIN_TABLE_BASE(ALP442_CHANNELS_IN_ANALOG_OFFSET),
		.prefix			= "Ana Capture",
		.access			= SNDRV_CTL_ELEM_ACCESS_READWRITE |
								SNDRV_CTL_ELEM_ACCESS_TLV_READ,
		.data.ampli = {
			.gains_scale = alpxxx_line_digital_gains_scale,
			.reg_gain_min	= ALP_AMPLIFIER_GAIN_MIN_REG,
			.reg_gain_max	= ALP_AMPLIFIER_GAIN_MAX_REG,
			.lines_count	= ALP442_CHANNELS_ANALOG_COUNT,
		},
	},
	{
		.type			= ALPX_CONTROL_TYPE_AMPLIFIER,
		.base			= ALPMC_AMPLI_IN_BASE +
					ALPMC_GAIN_TABLE_BASE(ALP442_CHANNELS_IN_AES_OFFSET),
		.prefix			= "AES Capture",
		.access			= SNDRV_CTL_ELEM_ACCESS_READWRITE |
								SNDRV_CTL_ELEM_ACCESS_TLV_READ,
		.data.ampli = {
			.gains_scale = alpxxx_line_digital_gains_scale,
			.reg_gain_min	= ALP_AMPLIFIER_GAIN_MIN_REG,
			.reg_gain_max	= ALP_AMPLIFIER_GAIN_MAX_REG,
			.lines_count	= ALP442_CHANNELS_AES_COUNT,
		},
	},
	{
		.type			= ALPX_CONTROL_TYPE_AMPLIFIER,
		.base			= ALPMC_AMPLI_OUT_BASE +
					ALPMC_GAIN_TABLE_BASE(ALP442_CHANNELS_OUT_ANALOG_OFFSET),
		.prefix			= "Ana Playback",
		.access			= SNDRV_CTL_ELEM_ACCESS_READWRITE |
								SNDRV_CTL_ELEM_ACCESS_TLV_READ,
		.data.ampli = {
			.gains_scale = alpxxx_line_digital_gains_scale,
			.reg_gain_min	= ALP_AMPLIFIER_GAIN_MIN_REG,
			.reg_gain_max	= ALP_AMPLIFIER_GAIN_MAX_REG,
			.lines_count	= ALP442_CHANNELS_ANALOG_COUNT,
		},
	},
	{
		.type			= ALPX_CONTROL_TYPE_AMPLIFIER,
		.base			= ALPMC_AMPLI_OUT_BASE +
					ALPMC_GAIN_TABLE_BASE(ALP442_CHANNELS_OUT_AES_OFFSET),
		.prefix			= "AES Playback",
		.access			= SNDRV_CTL_ELEM_ACCESS_READWRITE |
								SNDRV_CTL_ELEM_ACCESS_TLV_READ,
		.data.ampli = {
			.gains_scale = alpxxx_line_digital_gains_scale,
			.reg_gain_min	= ALP_AMPLIFIER_GAIN_MIN_REG,
			.reg_gain_max	= ALP_AMPLIFIER_GAIN_MAX_REG,
			.lines_count	= ALP442_CHANNELS_AES_COUNT,
		},
	},
	{
		.type			= ALPX_CONTROL_TYPE_AMPLIFIER,
		.base			= ALPMC_AMPLI_OUT_BASE +
					ALPMC_GAIN_TABLE_BASE(ALP442_CHANNELS_OUT_DAW_OFFSET),
		.prefix			= "DAW Playback",
		.access			= SNDRV_CTL_ELEM_ACCESS_READWRITE |
								SNDRV_CTL_ELEM_ACCESS_TLV_READ,
		.data.ampli = {
			.gains_scale = alpxxx_line_digital_gains_scale,
			.reg_gain_min	= ALP_AMPLIFIER_GAIN_MIN_REG,
			.reg_gain_max	= ALP_AMPLIFIER_GAIN_MAX_REG,
			.lines_count	= ALP442_CHANNELS_DAW_COUNT,
		},
	},
		/* Mixer */
	{
		.type			= ALPX_CONTROL_TYPE_MIXER,
		.base			= ALPMC_MIXER_BASE,
		.prefix			= "Mxr",
		.access			= SNDRV_CTL_ELEM_ACCESS_READWRITE |
								SNDRV_CTL_ELEM_ACCESS_TLV_READ,
		.data.mixer		= {
			.lines_count	= ALP442_MIXER_SIZE,
			.gains_scale = alpxxx_line_digital_gains_scale,
			.reg_gain_min	= ALP_AMPLIFIER_GAIN_MIN_REG,
			.reg_gain_max	= ALP_AMPLIFIER_GAIN_MAX_REG,
		},
	},
	/* Clock sources Read Only */
	{
		.type			= ALPX_CONTROL_TYPE_CHOICE,
		.base			= ALPMC_CLK_MANAGER_BASE,
		.prefix			= "Clk Eff Src",
		.access			= SNDRV_CTL_ELEM_ACCESS_READ,
		.data.choice		= {
			.offset		= ALPMC_CLK_MANAGER_CONFIG_REG,
			.mask		= ALPMC_CLK_MANAGER_CONFIG_CLK_SRC_MASK,
			.pos = ALPMC_CLK_MANAGER_CONFIG_CLK_SRC_POS,
			.entries		= alp442_control_choice_clk_src_entries,
			.entries_values	= alp442_control_choice_clk_src_entries_values,
			.entries_count	= ARRAY_SIZE(alp442_control_choice_clk_src_entries),
		},
	},
	
	/* Current Clock BASE Value Read Only */
	{
		.type			= ALPX_CONTROL_TYPE_CHOICE,
		.base			= ALPMC_CLK_MANAGER_BASE,
		.prefix			= "Clk Eff",
		.access			= SNDRV_CTL_ELEM_ACCESS_READ | 
								SNDRV_CTL_ELEM_ACCESS_VOLATILE,
		.data.choice		= {
			.offset		= ALPMC_CLK_MANAGER_CONFIG_REG,
			.mask		= ALPMC_CLK_MANAGER_CONFIG_CLK_CURRENT_VALUE_MASK,
			.pos = ALPMC_CLK_MANAGER_CONFIG_CLK_CURRENT_VALUE_POS,
			.entries		= alpxxx_control_choice_current_clk_values_entries,
			.entries_values	= alpxxx_control_choice_current_clk_values_entries_values,
			.entries_count	= ARRAY_SIZE(alpxxx_control_choice_current_clk_values_entries),
		},
	},
	
	/* Current Clock factor values Read Only, RESERVED to keep Ids order */
	{
		.type			= ALPX_CONTROL_RESERVED,
		.base			= ALPMC_CLK_MANAGER_BASE,
		.prefix			= "RESERVED",
		.access			= SNDRV_CTL_ELEM_ACCESS_READ,
	},
		/* Clock UP on fail over enabled flag */
	{
		.type			= ALPX_CONTROL_TYPE_FLAG,
		.base			= ALP_PROC_BASE,
		.prefix			= "Clk Src Up",
		.access			= SNDRV_CTL_ELEM_ACCESS_READWRITE,
		.data.flag		= {
			.offset		= ALP_PROC_FWCONFIG_REG,
			.mask		= ALP_PROC_FWCONFIG_CLKSRC_UP_MASK,
			.pos		= ALP_PROC_FWCONFIG_CLKSRC_UP_POS,
		},
	},
	/* Clock DOWN on fail over enabled flag */
	{
		.type			= ALPX_CONTROL_TYPE_FLAG,
		.base			= ALP_PROC_BASE,
		.prefix			= "Clk Src Down",
		.access			= SNDRV_CTL_ELEM_ACCESS_READWRITE,
		.data.flag		= {
			.offset		= ALP_PROC_FWCONFIG_REG,
			.mask		= ALP_PROC_FWCONFIG_CLKSRC_DOWN_MASK,
			.pos		= ALP_PROC_FWCONFIG_CLKSRC_DOWN_POS,
		},
	},
	/* Clock Failover priority 0 TOP*/
	{
		.type			= ALPX_CONTROL_TYPE_CHOICE,
		.base			= ALP_PROC_BASE,
		.prefix			= "Clk P0",
		.access			= SNDRV_CTL_ELEM_ACCESS_READWRITE,
		.data.choice		= {
			.offset		= ALP_PROC_CLK_SOURCE_PRIO_REG,
			.mask		= ALP_PROC_CLK_SOURCE_PRIO0_MASK,
			.pos			= ALP_PROC_CLK_SOURCE_PRIO0_POS,
			.entries		= alp442_control_choice_clk_src_entries,
			.entries_values	= alp442_control_choice_clk_src_entries_values,
			.entries_count	= ARRAY_SIZE(alp442_control_choice_clk_src_entries),
		},
	},
	/* Clock Failover priority 1 */
	{
		.type			= ALPX_CONTROL_TYPE_CHOICE,
		.base			= ALP_PROC_BASE,
		.prefix			= "Clk P1",
		.access			= SNDRV_CTL_ELEM_ACCESS_READWRITE,
		.data.choice		= {
			.offset		= ALP_PROC_CLK_SOURCE_PRIO_REG,
			.mask		= ALP_PROC_CLK_SOURCE_PRIO1_MASK,
			.pos			= ALP_PROC_CLK_SOURCE_PRIO1_POS,
			.entries		= alp442_control_choice_clk_src_entries,
			.entries_values	= alp442_control_choice_clk_src_entries_values,
			.entries_count	= ARRAY_SIZE(alp442_control_choice_clk_src_entries),
		},
	},
	/* Clock Failover priority 2*/
	{
		.type			= ALPX_CONTROL_TYPE_CHOICE,
		.base			= ALP_PROC_BASE,
		.prefix			= "Clk P2",
		.access			= SNDRV_CTL_ELEM_ACCESS_READWRITE,
		.data.choice		= {
			.offset		= ALP_PROC_CLK_SOURCE_PRIO_REG,
			.mask		= ALP_PROC_CLK_SOURCE_PRIO2_MASK,
			.pos			= ALP_PROC_CLK_SOURCE_PRIO2_POS,
			.entries		= alp442_control_choice_clk_src_entries,
			.entries_values	= alp442_control_choice_clk_src_entries_values,
			.entries_count	= ARRAY_SIZE(alp442_control_choice_clk_src_entries),
		},
	},
	/* Clock Failover priority 3*/
	{
		.type			= ALPX_CONTROL_TYPE_CHOICE,
		.base			= ALP_PROC_BASE,
		.prefix			= "Clk P3",
		.access			= SNDRV_CTL_ELEM_ACCESS_READWRITE,
		.data.choice		= {
			.offset		= ALP_PROC_CLK_SOURCE_PRIO_REG,
			.mask		= ALP_PROC_CLK_SOURCE_PRIO3_MASK,
			.pos			= ALP_PROC_CLK_SOURCE_PRIO3_POS,
			.entries		= alp442_control_choice_clk_src_entries,
			.entries_values	= alp442_control_choice_clk_src_entries_values,
			.entries_count	= ARRAY_SIZE(alp442_control_choice_clk_src_entries),
		},
	},
	/* Auto AES SRC disable */
	{
		.type			= ALPX_CONTROL_TYPE_FLAG,
		.base			= ALPMC_CODEC_CTRL_BASE,
		.prefix			= "AES SRC 1/2 Disable",
		.access			= SNDRV_CTL_ELEM_ACCESS_READWRITE,
		.data.flag		= {
			.offset		= ALPMC_CODEC_AES_SRC_CONTROL_REG,
			.mask		= ALPMC_CODEC_AES_SRC_1_2_MASK,
			.pos			= ALPMC_CODEC_AES_SRC_1_2_POS,
		},
	},
	{
		.type			= ALPX_CONTROL_TYPE_FLAG,
		.base			= ALPMC_CODEC_CTRL_BASE,
		.prefix			= "AES SRC 3/4 Disable",
		.access			= SNDRV_CTL_ELEM_ACCESS_READWRITE,
		.data.flag		= {
			.offset		= ALPMC_CODEC_AES_SRC_CONTROL_REG,
			.mask		= ALPMC_CODEC_AES_SRC_3_4_MASK,
			.pos			= ALPMC_CODEC_AES_SRC_3_4_POS,
		},
	},
	/* Codec Input Gain for LINE Option*/
	{
		.type			= ALPX_CONTROL_TYPE_ANALOG_EQ,
		.base			= ALPMC_CODEC_CTRL_BASE,
		.prefix			= "Codec Analog Capture",
		.access			= SNDRV_CTL_ELEM_ACCESS_READWRITE |
								SNDRV_CTL_ELEM_ACCESS_TLV_READ,
		.data.codec		= {
			.offset = ALPMC_CODEC_PGA_REGS,
			.gains_scale = alpmc_line_control_codec_gains_scale,
			.reg_gain_min	= ALPMC_LINE_ANALOG_GAIN_MIN_REG,
			.reg_gain_max	= ALPMC_LINE_ANALOG_GAIN_MAX_REG,
			.lines_count	= ALP442_CHANNELS_ANALOG_COUNT,
		},
	},
};

static struct alpx_variant alp442_line_variant __attribute__((unused)) = {
	.shortname			= "Alp442e",
	.longname			= "Alp 442e",
	.model				= ALPX_VARIANT_MODEL_ALP442,
	.mixername			= "Alp442e_Mix",
	.features			= ALPX_VARIANT_FEATURE_GPIOS,
	.control_descriptors		= alp442_line_control_descriptors,
	.control_descriptors_count	= ARRAY_SIZE(alp442_line_control_descriptors),

	.capture_hw			= &alp442_hardware_specs,
	.playback_hw			= &alp442_hardware_specs,
	
	.flash_golden_production_base = ALPxxx_FLASH_GOLDEN_PRODUCTION_BASE,
	
	.gpios = {/*Same as Alp882*/
	.base = ALPMC_GPIO_BASE,
	.inputs_reg_offset = ALPMC_GPIO_INPUT_REG,
	.inputs_qty = ALPMC_GPIO_INPUT_QTY,
	.outputs_reg_offset = ALPMC_GPIO_OUTPUT_REG,
	.outputs_qty = ALPMC_GPIO_OUTPUT_QTY,
	},
	
	.flash_partitions.partitions = alpx_mtd_partitions,
	.flash_partitions.qty = ARRAY_SIZE(alpx_mtd_partitions),
	.flash_partitions.qty_for_fw_update = 1,
};


/* Alp 442 - MIC  Variant definition */

static struct alpx_control_descriptor alp442_mic_control_descriptors[] = {
	/* Gain */
	{
		.type			= ALPX_CONTROL_TYPE_AMPLIFIER,
		.base			= ALPMC_AMPLI_IN_BASE +
					ALPMC_GAIN_TABLE_BASE(ALP442_CHANNELS_IN_DAW_OFFSET),
		.prefix			= "DAW Capture",
		.access			= SNDRV_CTL_ELEM_ACCESS_READWRITE |
								SNDRV_CTL_ELEM_ACCESS_TLV_READ,
		.data.ampli = {
			.gains_scale = alpxxx_line_digital_gains_scale,
			.reg_gain_min	= ALP_AMPLIFIER_GAIN_MIN_REG,
			.reg_gain_max	= ALP_AMPLIFIER_GAIN_MAX_REG,
			.lines_count	= ALP442_CHANNELS_DAW_COUNT,
		},
	},
	{
		.type			= ALPX_CONTROL_TYPE_AMPLIFIER,
		.base			= ALPMC_AMPLI_IN_BASE +
					ALPMC_GAIN_TABLE_BASE(ALP442_CHANNELS_IN_ANALOG_OFFSET),
		.prefix			= "Ana Capture",
		.access			= SNDRV_CTL_ELEM_ACCESS_READWRITE |
								SNDRV_CTL_ELEM_ACCESS_TLV_READ,
		.data.ampli = {
			.gains_scale = alpxxx_line_digital_gains_scale,
			.reg_gain_min	= ALP_AMPLIFIER_GAIN_MIN_REG,
			.reg_gain_max	= ALP_AMPLIFIER_GAIN_MAX_REG,
			.lines_count	= ALP442_CHANNELS_ANALOG_COUNT,
		},
	},
	{
		.type			= ALPX_CONTROL_TYPE_AMPLIFIER,
		.base			= ALPMC_AMPLI_IN_BASE +
					ALPMC_GAIN_TABLE_BASE(ALP442_CHANNELS_IN_AES_OFFSET),
		.prefix			= "AES Capture",
		.access			= SNDRV_CTL_ELEM_ACCESS_READWRITE |
								SNDRV_CTL_ELEM_ACCESS_TLV_READ,
		.data.ampli = {
			.gains_scale = alpxxx_line_digital_gains_scale,
			.reg_gain_min	= ALP_AMPLIFIER_GAIN_MIN_REG,
			.reg_gain_max	= ALP_AMPLIFIER_GAIN_MAX_REG,
			.lines_count	= ALP442_CHANNELS_AES_COUNT,
		},
	},
	{
		.type			= ALPX_CONTROL_TYPE_AMPLIFIER,
		.base			= ALPMC_AMPLI_OUT_BASE +
					ALPMC_GAIN_TABLE_BASE(ALP442_CHANNELS_OUT_ANALOG_OFFSET),
		.prefix			= "Ana Playback",
		.access			= SNDRV_CTL_ELEM_ACCESS_READWRITE |
								SNDRV_CTL_ELEM_ACCESS_TLV_READ,
		.data.ampli = {
			.gains_scale = alpxxx_line_digital_gains_scale,
			.reg_gain_min	= ALP_AMPLIFIER_GAIN_MIN_REG,
			.reg_gain_max	= ALP_AMPLIFIER_GAIN_MAX_REG,
			.lines_count	= ALP442_CHANNELS_ANALOG_COUNT,
		},
	},
	{/*a 882 with halved QTY*/
		.type			= ALPX_CONTROL_TYPE_AMPLIFIER,
		.base			= ALPMC_AMPLI_OUT_BASE +
					ALPMC_GAIN_TABLE_BASE(ALP442_CHANNELS_OUT_AES_OFFSET),
		.prefix			= "AES Playback",
		.access			= SNDRV_CTL_ELEM_ACCESS_READWRITE |
								SNDRV_CTL_ELEM_ACCESS_TLV_READ,
		.data.ampli = {
			.gains_scale = alpxxx_line_digital_gains_scale,
			.reg_gain_min	= ALP_AMPLIFIER_GAIN_MIN_REG,
			.reg_gain_max	= ALP_AMPLIFIER_GAIN_MAX_REG,
			.lines_count	= ALP442_CHANNELS_AES_COUNT,
		},
	},
	{/*a 882 with halved QTY*/
		.type			= ALPX_CONTROL_TYPE_AMPLIFIER,
		.base			= ALPMC_AMPLI_OUT_BASE +
					ALPMC_GAIN_TABLE_BASE(ALP442_CHANNELS_OUT_DAW_OFFSET),
		.prefix			= "DAW Playback",
		.access			= SNDRV_CTL_ELEM_ACCESS_READWRITE |
								SNDRV_CTL_ELEM_ACCESS_TLV_READ,
		.data.ampli = {
			.gains_scale = alpxxx_line_digital_gains_scale,
			.reg_gain_min	= ALP_AMPLIFIER_GAIN_MIN_REG,
			.reg_gain_max	= ALP_AMPLIFIER_GAIN_MAX_REG,
			.lines_count	= ALP442_CHANNELS_DAW_COUNT,
		},
	},
		/* Mixer a 882 with halved QTY Mixer : square*/
	{
		.type			= ALPX_CONTROL_TYPE_MIXER,
		.base			= ALPMC_MIXER_BASE,
		.prefix			= "Mxr",
		.access			= SNDRV_CTL_ELEM_ACCESS_READWRITE |
								SNDRV_CTL_ELEM_ACCESS_TLV_READ,
		.data.mixer		= {
			.lines_count	= ALP442_MIXER_SIZE,
			.gains_scale = alpxxx_line_digital_gains_scale,
			.reg_gain_min	= ALP_AMPLIFIER_GAIN_MIN_REG,
			.reg_gain_max	= ALP_AMPLIFIER_GAIN_MAX_REG,
		},
	},
	/* Clock sources Read Only As 882 except for AES due to 4 entries only */
	{
		.type			= ALPX_CONTROL_TYPE_CHOICE,
		.base			= ALPMC_CLK_MANAGER_BASE,
		.prefix			= "Clk Eff Src",
		.access			= SNDRV_CTL_ELEM_ACCESS_READ,
		.data.choice		= {
			.offset		= ALPMC_CLK_MANAGER_CONFIG_REG,
			.mask		= ALPMC_CLK_MANAGER_CONFIG_CLK_SRC_MASK,
			.pos = ALPMC_CLK_MANAGER_CONFIG_CLK_SRC_POS,
			.entries		= alp442_control_choice_clk_src_entries,
			.entries_values	= alp442_control_choice_clk_src_entries_values,
			.entries_count	= ARRAY_SIZE(alp442_control_choice_clk_src_entries),
		},
	},
	/* Current Clock Value Read Only */
	{
		.type			= ALPX_CONTROL_TYPE_CHOICE,
		.base			= ALPMC_CLK_MANAGER_BASE,
		.prefix			= "Clk Eff",
		.access			= SNDRV_CTL_ELEM_ACCESS_READ | 
								SNDRV_CTL_ELEM_ACCESS_VOLATILE,
		.data.choice		= {
			.offset		= ALPMC_CLK_MANAGER_CONFIG_REG,
			.mask		= ALPMC_CLK_MANAGER_CONFIG_CLK_CURRENT_VALUE_MASK,
			.pos = ALPMC_CLK_MANAGER_CONFIG_CLK_CURRENT_VALUE_POS,
			.entries		= alpxxx_control_choice_current_clk_values_entries,
			.entries_values	= alpxxx_control_choice_current_clk_values_entries_values,
			.entries_count	= ARRAY_SIZE(alpxxx_control_choice_current_clk_values_entries),
		},
	},
	
	/* Current Clock factor values Read Only, RESERVED now to keep ids order */
	{
		.type			= ALPX_CONTROL_RESERVED,
		.base			= ALPMC_CLK_MANAGER_BASE,
		.prefix			= "RESERVED",
		.access			= SNDRV_CTL_ELEM_ACCESS_READ,
	},
		/* Clock UP on fail over enabled flag */
	{
		.type			= ALPX_CONTROL_TYPE_FLAG,
		.base			= ALP_PROC_BASE,
		.prefix			= "Clk Src Up",
		.access			= SNDRV_CTL_ELEM_ACCESS_READWRITE,
		.data.flag		= {
			.offset		= ALP_PROC_FWCONFIG_REG,
			.mask		= ALP_PROC_FWCONFIG_CLKSRC_UP_MASK,
			.pos		= ALP_PROC_FWCONFIG_CLKSRC_UP_POS,
		},
	},
	/* Clock DOWN on fail over enabled flag */
	{
		.type			= ALPX_CONTROL_TYPE_FLAG,
		.base			= ALP_PROC_BASE,
		.prefix			= "Clk Src Down",
		.access			= SNDRV_CTL_ELEM_ACCESS_READWRITE,
		.data.flag		= {
			.offset		= ALP_PROC_FWCONFIG_REG,
			.mask		= ALP_PROC_FWCONFIG_CLKSRC_DOWN_MASK,
			.pos		= ALP_PROC_FWCONFIG_CLKSRC_DOWN_POS,
		},
	},
	/* Clock Failover priority 0 TOP*/
	{
		.type			= ALPX_CONTROL_TYPE_CHOICE,
		.base			= ALP_PROC_BASE,
		.prefix			= "Clk P0",
		.access			= SNDRV_CTL_ELEM_ACCESS_READWRITE,
		.data.choice		= {
			.offset		= ALP_PROC_CLK_SOURCE_PRIO_REG,
			.mask		= ALP_PROC_CLK_SOURCE_PRIO0_MASK,
			.pos			= ALP_PROC_CLK_SOURCE_PRIO0_POS,
			.entries		= alp442_control_choice_clk_src_entries,
			.entries_values	= alp442_control_choice_clk_src_entries_values,
			.entries_count	= ARRAY_SIZE(alp442_control_choice_clk_src_entries),
		},
	},
	/* Clock Failover priority 1 */
	{
		.type			= ALPX_CONTROL_TYPE_CHOICE,
		.base			= ALP_PROC_BASE,
		.prefix			= "Clk P1",
		.access			= SNDRV_CTL_ELEM_ACCESS_READWRITE,
		.data.choice		= {
			.offset		= ALP_PROC_CLK_SOURCE_PRIO_REG,
			.mask		= ALP_PROC_CLK_SOURCE_PRIO1_MASK,
			.pos			= ALP_PROC_CLK_SOURCE_PRIO1_POS,
			.entries		= alp442_control_choice_clk_src_entries,
			.entries_values	= alp442_control_choice_clk_src_entries_values,
			.entries_count	= ARRAY_SIZE(alp442_control_choice_clk_src_entries),
		},
	},
	/* Clock Failover priority 2*/
	{
		.type			= ALPX_CONTROL_TYPE_CHOICE,
		.base			= ALP_PROC_BASE,
		.prefix			= "Clk P2",
		.access			= SNDRV_CTL_ELEM_ACCESS_READWRITE,
		.data.choice		= {
			.offset		= ALP_PROC_CLK_SOURCE_PRIO_REG,
			.mask		= ALP_PROC_CLK_SOURCE_PRIO2_MASK,
			.pos			= ALP_PROC_CLK_SOURCE_PRIO2_POS,
			.entries		= alp442_control_choice_clk_src_entries,
			.entries_values	= alp442_control_choice_clk_src_entries_values,
			.entries_count	= ARRAY_SIZE(alp442_control_choice_clk_src_entries),
		},
	},
	/* Clock Failover priority 3*/
	{
		.type			= ALPX_CONTROL_TYPE_CHOICE,
		.base			= ALP_PROC_BASE,
		.prefix			= "Clk P3",
		.access			= SNDRV_CTL_ELEM_ACCESS_READWRITE,
		.data.choice		= {
			.offset		= ALP_PROC_CLK_SOURCE_PRIO_REG,
			.mask		= ALP_PROC_CLK_SOURCE_PRIO3_MASK,
			.pos			= ALP_PROC_CLK_SOURCE_PRIO3_POS,
			.entries		= alp442_control_choice_clk_src_entries,
			.entries_values	= alp442_control_choice_clk_src_entries_values,
			.entries_count	= ARRAY_SIZE(alp442_control_choice_clk_src_entries),
		},
	},
	/* Auto AES SRC disable SAME as Alp882 except for qty*/
	{
		.type			= ALPX_CONTROL_TYPE_FLAG,
		.base			= ALPMC_CODEC_CTRL_BASE,
		.prefix			= "AES SRC 1/2 Disable",
		.access			= SNDRV_CTL_ELEM_ACCESS_READWRITE,
		.data.flag		= {
			.offset		= ALPMC_CODEC_AES_SRC_CONTROL_REG,
			.mask		= ALPMC_CODEC_AES_SRC_1_2_MASK,
			.pos			= ALPMC_CODEC_AES_SRC_1_2_POS,
		},
	},
	{
		.type			= ALPX_CONTROL_TYPE_FLAG,
		.base			= ALPMC_CODEC_CTRL_BASE,
		.prefix			= "AES SRC 3/4 Disable",
		.access			= SNDRV_CTL_ELEM_ACCESS_READWRITE,
		.data.flag		= {
			.offset		= ALPMC_CODEC_AES_SRC_CONTROL_REG,
			.mask		= ALPMC_CODEC_AES_SRC_3_4_MASK,
			.pos			= ALPMC_CODEC_AES_SRC_3_4_POS,
		},
	},
	/* Codec Input Gain for MIC Option SAME as 882 execpt for qty*/
	{
		.type			= ALPX_CONTROL_TYPE_ANALOG_EQ,
		.base			= ALPMC_CODEC_CTRL_BASE,
		.prefix			= "Codec MIC Analog Capture",
		.access			= SNDRV_CTL_ELEM_ACCESS_READWRITE |
								SNDRV_CTL_ELEM_ACCESS_TLV_READ,
		.data.codec		= {
			.offset = ALPMC_CODEC_PGA_REGS,
			.gains_scale = alpmc_mic_control_codec_gains_scale,
			.reg_gain_min	= ALPMC_MIC_ANALOG_GAIN_MIN_REG,
			.reg_gain_max	= ALPMC_MIC_ANALOG_GAIN_MAX_REG,
			.lines_count	= ALP442_CHANNELS_ANALOG_COUNT,
		},
	},
		/** MIC Phantoms SAME as 882 except for qty **/
	/* MIC Phantom 1 */
	{
		.type			= ALPX_CONTROL_TYPE_FLAG,
		.base			= ALPMC_CODEC_CTRL_BASE,
		.prefix			= "McPh1",
		.access			= SNDRV_CTL_ELEM_ACCESS_READWRITE,
		.data.mic_flags		= {
			.offset		= ALPMC_INPUT_PARAMS_REG,
			.mask		= ALPMC_MIC_INPUT_PH_1_MASK,
			.pos		= ALPMC_MIC_INPUT_PH_1_POS,
		},
	},
	/* MIC Phantom 2 */
	{
		.type			= ALPX_CONTROL_TYPE_FLAG,
		.base			= ALPMC_CODEC_CTRL_BASE,
		.prefix			= "McPh2",
		.access			= SNDRV_CTL_ELEM_ACCESS_READWRITE,
		.data.mic_flags		= {
			.offset		= ALPMC_INPUT_PARAMS_REG,
			.mask		= ALPMC_MIC_INPUT_PH_2_MASK,
			.pos		= ALPMC_MIC_INPUT_PH_2_POS,
		},
	},
	/* MIC Phantom 3 */
	{
		.type			= ALPX_CONTROL_TYPE_FLAG,
		.base			= ALPMC_CODEC_CTRL_BASE,
		.prefix			= "McPh3",
		.access			= SNDRV_CTL_ELEM_ACCESS_READWRITE,
		.data.mic_flags		= {
			.offset		= ALPMC_INPUT_PARAMS_REG,
			.mask		= ALPMC_MIC_INPUT_PH_3_MASK,
			.pos		= ALPMC_MIC_INPUT_PH_3_POS,
		},
	},
	/* MIC Phantom 4 */
	{
		.type			= ALPX_CONTROL_TYPE_FLAG,
		.base			= ALPMC_CODEC_CTRL_BASE,
		.prefix			= "McPh4",
		.access			= SNDRV_CTL_ELEM_ACCESS_READWRITE,
		.data.mic_flags		= {
			.offset		= ALPMC_INPUT_PARAMS_REG,
			.mask		= ALPMC_MIC_INPUT_PH_4_MASK,
			.pos			= ALPMC_MIC_INPUT_PH_4_POS,
		},
	},
};


static struct alpx_variant alp442_mic_variant __attribute__((unused)) = {
	.shortname			= "Alp442e-MIC",
	.longname			= "Alp 442e MIC",
	.model				= ALPX_VARIANT_MODEL_ALP442_MIC,
	.mixername			= "Alp442e_MIC_Mix",
	.features			= ALPX_VARIANT_FEATURE_GPIOS,
	.control_descriptors		= alp442_mic_control_descriptors,
	.control_descriptors_count	= ARRAY_SIZE(alp442_mic_control_descriptors),

	.capture_hw			= &alp442_hardware_specs,
	.playback_hw			= &alp442_hardware_specs,
	
	.flash_golden_production_base = ALPxxx_FLASH_GOLDEN_PRODUCTION_BASE,
	
	.gpios = {/* Same as 882 */
	.base = ALPMC_GPIO_BASE,
	.inputs_reg_offset = ALPMC_GPIO_INPUT_REG, 
	.inputs_qty = ALPMC_GPIO_INPUT_QTY,
	.outputs_reg_offset = ALPMC_GPIO_OUTPUT_REG,
	.outputs_qty = ALPMC_GPIO_OUTPUT_QTY,
	},
	
	.flash_partitions.partitions = alpx_mtd_partitions,
	.flash_partitions.qty = ARRAY_SIZE(alpx_mtd_partitions),
	.flash_partitions.qty_for_fw_update = 1,
};


#endif /* _ALPX_VARIANTS_MC_H_ */